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公开(公告)号:US12048165B2
公开(公告)日:2024-07-23
申请号:US16914140
申请日:2020-06-26
申请人: Intel Corporation
发明人: Nazila Haratipour , Sou-Chi Chang , Shriram Shivaraman , I-Cheng Tung , Tobias Brown-Heft , Devin R. Merrill , Che-Yun Lin , Seung Hoon Sung , Jack Kavalieros , Uygar Avci , Matthew V. Metz
CPC分类号: H10B53/00 , G11C11/221 , H01G4/008 , H01L27/0805 , H01L28/65 , H10B53/10
摘要: An integrated circuit capacitor structure, includes a first electrode includes a cylindrical column, a ferroelectric layer around an exterior sidewall of the cylindrical column and a plurality of outer electrodes. The plurality of outer electrodes include a first outer electrode laterally adjacent to a first portion of an exterior of the ferroelectric layer and a second outer electrode laterally adjacent to a second portion of the exterior of the ferroelectric layer, wherein the second outer electrode is above the first outer electrode.
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公开(公告)号:US11935574B2
公开(公告)日:2024-03-19
申请号:US17496564
申请日:2021-10-07
发明人: Michael Mutch , Ashonita A. Chavan , Sameer Chhajed , Beth R. Cook , Kamal Kumar Muthukrishnan , Durai Vishak Nirmal Ramaswamy , Lance Williamson
CPC分类号: G11C11/221 , H01L28/60 , H10B53/00
摘要: A memory cell comprises a capacitor comprising a first capacitor electrode having laterally-spaced walls, a second capacitor electrode comprising a portion above the first capacitor electrode, and capacitor insulator material between the second capacitor electrode and the first capacitor electrode. The capacitor comprises an intrinsic current leakage path from one of the first and second capacitor electrodes to the other through the capacitor insulator material. A parallel current leakage path is between the second capacitor electrode and the first capacitor electrode. The parallel current leakage path is circuit-parallel with the intrinsic current leakage path, of lower total resistance than the intrinsic current leakage path, and comprises leaker material that is everywhere laterally-outward of laterally-innermost surfaces of the laterally-spaced walls of the first capacitor electrode. Other embodiments, including methods, are disclosed.
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公开(公告)号:US11849588B2
公开(公告)日:2023-12-19
申请号:US17712543
申请日:2022-04-04
发明人: Fu-Chen Chang , Kuo-Chi Tu , Tzu-Yu Chen , Sheng-Hung Shih
摘要: A method of forming a semiconductor device includes forming an inter-metal dielectric layer over a substrate; forming a first conductive line embedded in the inter-metal dielectric layer; forming a dielectric structure over the inter-metal dielectric layer and the first conductive line; etching the dielectric structure until the first conductive line is exposed; forming a bottom electrode layer on the exposed first conductive line such that the bottom electrode layer has an U-shaped when viewed in a cross section; forming a ferroelectric layer over the bottom electrode layer; forming a top electrode layer over the ferroelectric layer.
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公开(公告)号:US20230399749A1
公开(公告)日:2023-12-14
申请号:US18455941
申请日:2023-08-25
发明人: Bo-Eun PARK , Jooho LEE , Yongsung KIM , Jeonggyu SONG
IPC分类号: C23C16/56 , C23C16/455 , C23C14/58 , C23C16/40 , C01G27/02 , C23C14/08 , H10B51/00 , H10B53/00
CPC分类号: C23C16/56 , C23C16/45525 , C23C14/5806 , C23C16/40 , C01G27/02 , C23C14/08 , H10B51/00 , H10B53/00 , C01P2004/24 , C01P2002/72 , C01P2006/40 , C01P2002/76
摘要: A thin film structure includes a first conductive layer, a dielectric material layer on the first conductive layer, and an upper layer on the dielectric material layer. The dielectric material layer including HfxA1-xO2 satisfies at least one of a first condition and a second condition. In the first condition the dielectric material layer is formed to a thickness of 5 nm or less and in the second condition the x in HfxA1-xO2 is in a range of 0.3 to 0.5.
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公开(公告)号:US20230395690A1
公开(公告)日:2023-12-07
申请号:US18235740
申请日:2023-08-18
发明人: Albert Liao , Manzar Siddik
CPC分类号: H01L29/516 , G11C11/221 , H01L29/40111 , G11C11/223 , H01L28/65 , H01L28/55 , H01L28/40 , H10B53/00 , H10B53/30 , H01L2924/1441
摘要: Some embodiments include ferroelectric assemblies. Some embodiments include a capacitor which has ferroelectric insulative material between a first electrode and a second electrode. The capacitor also has a metal oxide between the second electrode and the ferroelectric insulative material. The metal oxide has a thickness of less than or equal to about 30 Å. Some embodiments include a method of forming an assembly. A first capacitor electrode is formed over a semiconductor-containing base. Ferroelectric insulative material is formed over the first electrode. A metal-containing material is formed over the ferroelectric insulative material. The metal-containing material is oxidized to form a metal oxide from the metal-containing material. A second electrode is formed over the metal oxide.
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公开(公告)号:US20240206188A1
公开(公告)日:2024-06-20
申请号:US18590282
申请日:2024-02-28
发明人: Sanghun JEON
CPC分类号: H10B53/00 , G11C11/221 , H01L29/516 , H01L29/78391 , H10B53/20
摘要: The present invention relates to ferroelectric capacitors, transistors, memory device, and method of manufacturing ferroelectric devices. The ferroelectric capacitor includes a first electrode, a second electrode facing the first electrode, a ferroelectric layer between the first electrode and the second electrode, and an interfacial layer between the ferroelectric layer and the first electrode or between the ferroelectric layer and the second electrode. The ferroelectric layer includes hafnium-based oxide. The interfacial layer includes HfO2.
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公开(公告)号:US11961910B2
公开(公告)日:2024-04-16
申请号:US17002670
申请日:2020-08-25
CPC分类号: H01L29/78391 , H01G4/005 , H01L29/22 , H10B51/00 , H10B53/00
摘要: A ferroelectric capacitor or a ferroelectric transistor may include a first metal layer having a first metal having a first work function, and a second metal layer having a second metal having a second work function. The capacitor may also include a a vertical electrode and a ferroelectric material that surrounds the vertical electrode and forms a plurality of switching regions in the ferroelectric material. The transistor may include a vertical channel, a vertical buffer layer that surround the vertical channel, and a ferroelectric material that surrounds the vertical buffer layer and forms a plurality of gate regions in the ferroelectric material.
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公开(公告)号:US11908887B2
公开(公告)日:2024-02-20
申请号:US17307592
申请日:2021-05-04
发明人: Jaeho Lee , Boeun Park , Younggeun Park , Jooho Lee
摘要: Provided are a capacitor and a semiconductor device including the capacitor. The capacitor includes a first electrode; a plurality of dielectric films on the first electrode in a sequential series, the plurality of dielectric layers having different conductances from each other; and a second electrode on the plurality of dielectric films, wherein the capacitor has a capacitance which converges to a capacitance of one of the plurality of dielectric films.
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公开(公告)号:USRE49620E1
公开(公告)日:2023-08-22
申请号:US16901132
申请日:2020-06-15
申请人: Fudan University
发明人: Anquan Jiang , Wenping Geng
IPC分类号: G11C11/22 , H01L27/11502 , H01L49/02 , H10B53/00
CPC分类号: G11C11/2275 , G11C11/22 , G11C11/2273 , H01L28/55 , H01L28/56 , H10B53/00
摘要: Disclosed is a non-destructive large current-readout ferroelectric single-crystal thin film memory as well as a method of preparing the ferroelectric memory and a method of operating the ferroelectric memory. The large current-readout ferroelectric single-crystal thin film memory comprises a ferroelectric storage layer, which is a ferroelectric single-crystal storage layer. The non-destructive readout ferroelectric memory has a greatly increased read current in an on-state, and moreover, the data retention performance and data endurance performance are improved.
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公开(公告)号:US11716083B1
公开(公告)日:2023-08-01
申请号:US17645840
申请日:2021-12-23
发明人: Sasikanth Manipatruni , Nabil Imam , Ikenna Odinaka , Rafael Rios , Rajeev Kumar Dokania , Amrita Mathuriya
CPC分类号: H03K19/0027 , H01L28/55 , H01L28/65 , H10B53/00
摘要: Asynchronous circuits implemented using threshold gate(s) and/or majority gate(s) (or minority gate(s)) are described. The new class of asynchronous circuits can operate at lower power supply levels (e.g., less than 1V on advanced technology nodes) because stack of devices between a supply node and ground are significantly reduced compared to traditional asynchronous circuits. The asynchronous circuits here result in area reduction (e.g., 3× reduction compared to traditional asynchronous circuits) and provide higher throughput/mm2 (e.g., 2× higher throughput compared to traditional asynchronous circuits). The threshold gate(s), majority/minority gate(s) can be implemented using capacitive input circuits. The capacitors can have linear dielectric or non-linear polar material as dielectric.
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