公开(公告)号：US20110040912A1

公开(公告)日：2011-02-17

申请号：US11575003

申请日：2004-09-10

申请人： Kostantin Godin ,  Moshe Anschel ,  Jacob Efrat ,  Itay Peled ,  Reuven Badash ,  Asher Bastaker ,  Dvir Rune Peleg ,  Ziv Zamsky

发明人： Kostantin Godin ,  Moshe Anschel ,  Jacob Efrat ,  Itay Peled ,  Reuven Badash ,  Asher Bastaker ,  Dvir Rune Peleg ,  Ziv Zamsky

IPC分类号： G06F13/40 ,  G06F13/36

CPC分类号： G06F13/4013 ,  G06F13/4018

摘要： Apparatus and method for bus matching. The method includes: receiving data transfer characteristics at a first endian mode and at a second endian mode; determining a connectivity of multiple devices to an interfacing bus in response to the data transfer characteristics and in response to a relationship between a width of the interfacing bus and a width of each device interface; wherein at least one device interface is connected in parallel to multiple interfacing bus portions; and configuring a control logic such as to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to the connectivity. The apparatus includes: an interfacing bus characterized by an interfacing bus width; a master device, connected to the interfacing bus, whereas the master device includes a master device interface; multiple slave devices, each slave device connected to the interfacing bus and includes a slave device interface; wherein at least one slave device interface is connected in parallel to multiple interfacing bus portions; and control logic, connected to the interfacing bus and to the master device, the control logic is adapted to provide control signals representative of a transfer of data over the interfacing bus; whereas the control logic is configured in response to a connectivity of the multiple slave devices to the interfacing bus; whereas said connectivity is responsive to data transfer characteristics and is responsive to relationships between a width of the interfacing bus and a width of each device interface.

摘要翻译： 总线匹配的装置和方法。 该方法包括：在第一端模式和第二端模式下接收数据传输特性; 响应于数据传输特性和响应于接口总线的宽度与每个设备接口的宽度之间的关系，确定多个设备到接口总线的连接性; 其中至少一个设备接口并联连接到多个接口总线部分; 以及配置控制逻辑，例如提供表示在接口总线上传送数据的控制信号; 而控制逻辑被配置为响应于连接。 该装置包括：接口总线，其特征在于接口总线宽度; 主设备，连接到接口总线，而主设备包括主设备接口; 多个从设备，每个从设备连接到接口总线并且包括从设备接口; 其中至少一个从设备接口并联连接到多个接口总线部分; 以及连接到接口总线和主设备的控制逻辑，控制逻辑适于提供表示通过接口总线传送数据的控制信号; 而控制逻辑被配置为响应于多个从设备到接口总线的连接; 而所述连接性响应于数据传输特性，并且响应于接口总线的宽度与每个设备接口的宽度之间的关系。

公开(公告)号：US08117400B2

公开(公告)日：2012-02-14

申请号：US12446413

申请日：2006-10-20

申请人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

发明人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

IPC分类号： G06F12/00

CPC分类号： G06F12/0859 ,  G06F9/3834 ,  G06F12/0862

摘要： A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.

摘要翻译： 一种用于获取信息单元的设备和方法，所述方法包括：通过所述信息单元的可高速缓存操作来接收执行写入的请求; 从数据中取出取出单元，其中取出单元连接到高速缓存模块和高级存储单元; 当所述提取单元为空时，确定所述高速缓存模块是否存储所述信息单元的旧版本; 以及响应于所述确定而响应于所述高速缓存模块选择性地将所述信息单元写入所述高速缓存模块。

公开(公告)号：US20100325366A1

公开(公告)日：2010-12-23

申请号：US12446413

申请日：2006-10-20

申请人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

发明人： Ziv Zamsky ,  Moshe Anschel ,  Alon Eldar ,  Dmitry Flat ,  Kostantin Godin ,  Itay Peled ,  Dvir Peleg

IPC分类号： G06F12/08

CPC分类号： G06F12/0859 ,  G06F9/3834 ,  G06F12/0862

摘要： A device and a method for fetching an information unit, the method includes: receiving a request to execute a write through cacheable operation of the information unit; emptying a fetch unit from data, wherein the fetch unit is connected to a cache module and to a high level memory unit; determining, when the fetch unit is empty, whether the cache module stores an older version of the information unit; and selectively writing the information unit to the cache module in response to the cache module in response to the determination.

摘要翻译： 一种用于获取信息单元的设备和方法，所述方法包括：通过所述信息单元的可高速缓存操作来接收执行写入的请求; 从数据中取出取出单元，其中取出单元连接到高速缓存模块和高级存储单元; 当所述提取单元为空时，确定所述高速缓存模块是否存储所述信息单元的旧版本; 以及响应于所述确定而响应于所述高速缓存模块选择性地将所述信息单元写入所述高速缓存模块。

公开(公告)号：US08886895B2

公开(公告)日：2014-11-11

申请号：US10940121

申请日：2004-09-14

申请人： Itay Peled ,  Moshe Anschel ,  Jacob Efrat ,  Alon Eldar ,  Ziv Zamsky

发明人： Itay Peled ,  Moshe Anschel ,  Jacob Efrat ,  Alon Eldar ,  Ziv Zamsky

IPC分类号： G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0859 ,  G06F12/0862

摘要： A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.

摘要翻译： 一种用于响应于危险指示信息获取信息的方法，所述方法包括：（i）将危险指示信息与被提取到所述缓存模块的至少一个信息单元相关联; （ii）接收执行取出操作的请求; 以及（iii）响应于所述危险指示信息以及响应于与所述至少一个信息单元相关联的脏信息，确定是否将至少一个信息单元提取给所述高速缓存模块。

公开(公告)号：US20060059312A1

公开(公告)日：2006-03-16

申请号：US10940121

申请日：2004-09-14

申请人： Itay Peled ,  Moshe Anschel ,  Jacob Efrat ,  Alon Eldar ,  Ziv Zamsky

发明人： Itay Peled ,  Moshe Anschel ,  Jacob Efrat ,  Alon Eldar ,  Ziv Zamsky

IPC分类号： G06F12/00

CPC分类号： G06F12/0859 ,  G06F12/0862

摘要： A method for fetching information in response to hazard indication information, the method includes: (i) associating hazard indication information to at least one information unit that is being fetched to the cache module; (ii) receiving a request to perform a fetch operation; and (iii) determining whether to fetch at least one information unit to the cache module in response to the hazard indication information and in response to dirty information associated with the at least one information unit.

摘要翻译： 一种用于响应于危险指示信息获取信息的方法，所述方法包括：（i）将危险指示信息与被提取到所述缓存模块的至少一个信息单元相关联; （ii）接收执行取出操作的请求; 以及（iii）响应于所述危险指示信息以及响应于与所述至少一个信息单元相关联的脏信息，确定是否将至少一个信息单元提取给所述高速缓存模块。

公开(公告)号：US07620760B2

公开(公告)日：2009-11-17

申请号：US11815189

申请日：2005-02-07

申请人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Leonid Rabinovich ,  Noam Sivan ,  Eitan Zmora ,  Ziv Zamsky

发明人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Leonid Rabinovich ,  Noam Sivan ,  Eitan Zmora ,  Ziv Zamsky

IPC分类号： G06F13/36

CPC分类号： H03K19/0008

摘要： A device that includes: a first bus, connected between a first logic and a first circuit; a group of second buses connected between the first logic and between multiple non-high impedance circuit access logics associated with multiple circuits; wherein each circuit access logic is adapted to: (i) provide to the first logic, a circuit write value during a circuit writing period and during an idle period that follows the circuit writing period and ends when another circuit is allowed to write; and (ii) provide a default value when another circuit is allowed to write; and wherein the first logic is adapted to alter a state of the first bus in response to a change between two consecutive circuit write values.

摘要翻译： 一种装置，包括：连接在第一逻辑和第一电路之间的第一总线; 连接在第一逻辑和与多个电路相关联的多个非高阻抗电路访问逻辑之间的一组第二总线; 其中每个电路访问逻辑适于：（i）在电路写入周期期间和在电路写入周期之后的空闲周期期间向第一逻辑提供电路写入值，并且当允许另一个电路写入时结束; 和（ii）当允许另一个电路写入时提供默认值; 并且其中所述第一逻辑适于响应于两个连续电路写入值之间的变化而改变所述第一总线的状态。

公开(公告)号：US20060069877A1

公开(公告)日：2006-03-30

申请号：US10955220

申请日：2004-09-30

申请人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Zvika Rozenshein ,  Ziv Zamsky

发明人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Zvika Rozenshein ,  Ziv Zamsky

IPC分类号： G06F12/00

CPC分类号： G06F12/0859 ,  G06F12/0862 ,  G06F12/0879 ,  G06F13/28

摘要： Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) logic, adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller, connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the first and the second mandatory data units.

摘要翻译： 用于向高速缓存模块提供信息的设备和方法包括：（i）连接到高速缓存模块的至少一个处理器，用于发起从缓存模块检索第一和第二数据的第一和第二请求 单元; （ii）适于接收请求并确定第一和第二数据单元是否是强制性数据单元的逻辑; 连接到所述高速缓存模块的控制器，适于在所述单次提取突发期间检索到的存储器空间包括所述第一和第二强制性数据单元时启动单个提取突发，并且如果存储器空间 在单个提取突发期间可检索不包括第一和第二强制数据单元。

公开(公告)号：US07434009B2

公开(公告)日：2008-10-07

申请号：US10955220

申请日：2004-09-30

申请人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Zvika Rozenshein ,  Ziv Zamsky

发明人： Kostantin Godin ,  Moshe Anschel ,  Yacov Efrat ,  Zvika Rozenshein ,  Ziv Zamsky

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F12/0859 ,  G06F12/0862 ,  G06F12/0879 ,  G06F13/28

摘要： Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) logic, adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller, connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the first and the second mandatory data units.

摘要翻译： 用于向高速缓存模块提供信息的设备和方法包括：（i）连接到高速缓存模块的至少一个处理器，用于发起从缓存模块检索第一和第二数据的第一和第二请求 单元; （ii）适于接收请求并确定第一和第二数据单元是否是强制性数据单元的逻辑; 连接到所述高速缓存模块的控制器，适于在所述单次提取突发期间检索到的存储器空间包括所述第一和第二强制性数据单元时启动单个提取突发，并且如果存储器空间 在单个提取突发期间可检索不包括第一和第二强制数据单元。

公开(公告)号：US08006015B2

公开(公告)日：2011-08-23

申请号：US12514007

申请日：2006-11-08

申请人： Yaki Devilla ,  Moshe Anschel ,  Kostantin Godin ,  Amit Gur ,  Itay Peled

发明人： Yaki Devilla ,  Moshe Anschel ,  Kostantin Godin ,  Amit Gur ,  Itay Peled

IPC分类号： G06F12/00 ,  G06F13/14 ,  G06F13/38 ,  G06F13/00 ,  G06F9/34

CPC分类号： G06F13/36 ,  G06F13/1605

摘要： A device and a method for managing access requests, the method includes: (i) receiving, from a master component coupled to a master bus, multiple access requests to access a slave component over a pipelined slave bus; acknowledging a received access request if: (a) at least an inter-access request delay period lapsed from a last acknowledgement of an access request; (b) an amount of pending acknowledged access requests is below a threshold; wherein the threshold is determined in response to a pipeline depth of the pipelined slave bus; (c) the received access request is valid; wherein a validity of an access request is responsive to a reception of an access request cancellation request; and (ii) providing information from the slave component, in response to at least one acknowledged access request.

摘要翻译： 一种用于管理访问请求的装置和方法，所述方法包括：（i）从耦合到主总线的主组件接收多个访问请求以通过流水线从属总线访问从组件; 在以下情况下确认所接收的访问请求：（a）至少从访问请求的最后确认过去的访问间请求延迟时间; （b）等待确认的访问请求的数量低于阈值; 其中所述阈值响应于所述流水线从属总线的流水线深度被确定; （c）接收到的访问请求是有效的; 其中访问请求的有效性响应于访问请求取消请求的接收; 以及（ii）响应于至少一个确认的访问请求，从所述从属组件提供信息。

公开(公告)号：US08095769B2

公开(公告)日：2012-01-10

申请号：US12194273

申请日：2008-08-19

申请人： Rotem Porat ,  Moshe Anschel ,  Itay Peled ,  Erez Steinberg ,  Ziv Zamsky

发明人： Rotem Porat ,  Moshe Anschel ,  Itay Peled ,  Erez Steinberg ,  Ziv Zamsky

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/26 ,  G06F9/34

CPC分类号： G06F12/0292 ,  G06F12/1441 ,  Y02D10/13

摘要： A method for address comparison, the method includes: (i) receiving an input address; (ii) determining whether the input address is within a memory segment out of a group of memory segments by comparing, in parallel, the input address to memory segment boundaries of each memory segment of the group; (iii) wherein a comparison between the input address and a memory segment boundary comprises: (a) applying a XOR operation on bits of a most significant portion of the input address and corresponding bits of a most significant portion of the memory segment boundary; (b) ignoring bits of a least significant portion of the input address and corresponding bits of a least significant portion of the memory segment boundary; and (c) comparing, by utilizing a set of full comparators, between bits of an intermediate portion of the input address and corresponding bits of an intermediate portion of the memory segment boundary; wherein a location of bits that form the intermediate portion of the input address and of the memory segment boundary is selected in response to an alignment restriction imposed on the memory segment, to a size of the memory segment and in response to a boundary restriction imposed on the memory segment.

摘要翻译： 一种用于地址比较的方法，所述方法包括：（i）接收输入地址; （ii）并行地将所述组的每个存储器段的输入地址与存储器段边界进行比较来确定所述输入地址是否在一组存储器段内的存储器段内; （iii）其中输入地址和存储器段边界之间的比较包括：（a）对输入地址的最高有效部分的比特和存储器段边界的最高有效部分的相应比特应用异或运算; （b）忽略输入地址的最低有效部分的位和存储器段边界的最低有效部分的对应位; 以及（c）通过利用一组全比较器比较输入地址的中间部分的位与存储器段边界的中间部分的相应位之间的比较; 其中响应于对所述存储器段施加的对准限制而选择形成所述输入地址和所述存储器段边界的中间部分的位的位置，以及对所述存储器段的大小以及响应于对所述存储器段边界施加的边界限制 内存段。