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19 条记录 (耗时 0.023 秒)

    Digital broadcast receiver
    1.
    发明申请
    Digital broadcast receiver 审中-公开
    数字广播接收机

    公开(公告)号：US20060164563A1

    公开(公告)日：2006-07-27

    申请号：US10553738

    申请日：2004-06-15

    申请人： Kou Watanabe ,  Daisuke Hayashi ,  Hisaya Kato ,  Tetsuya Yagi

    发明人： Kou Watanabe ,  Daisuke Hayashi ,  Hisaya Kato ,  Tetsuya Yagi

    IPC分类号： H04N7/173 ,  H04N5/50 ,  H04N5/08 ,  H04N7/16

    CPC分类号： H03G3/3068 ,  H03G3/3089 ,  H04N5/4401 ,  H04N5/52

    摘要： A tuner has a dual AGC function, and frequency-converts an input signal into an IF signal. An orthogonal detector calculates a complex signal from the IF signal. A demodulator demodulates a digital signal from the complex signals. An error corrector corrects the error of the digital signal. A signal level detector calculates a level judgment signal from the IF signal. A demodulation level detector detects a signal level of a demodulation signal on a desired band from an output signal of the demodulator. When a demodulation level judgment unit generates a judgment signal representing an influence from interference waves in adjacent channel affecting on a signal on the desired band from the demodulation signal, a control signal generator feeds back a gain control signal to the tuner in accordance with the judgment signal.

    摘要翻译： 调谐器具有双AGC功能，并将输入信号频率转换成IF信号。 正交检波器计算来自IF信号的复信号。 解调器解调来自复信号的数字信号。 误差校正器校正数字信号的误差。 信号电平检测器从IF信号计算电平判断信号。 解调电平检测器从解调器的输出信号检测期望频带上的解调信号的信号电平。 当解调电平判断单元从解调信号产生表示影响相邻信道中的信号的干扰波的影响的判断信号时，控制信号发生器根据判断反馈增益控制信号给调谐器 信号。

    Method and device for forming a layered product having a bent over edge
    4.
    发明授权
    Method and device for forming a layered product having a bent over edge 有权
    用于形成具有弯曲边缘的层叠产品的方法和装置

    公开(公告)号：US07842151B2

    公开(公告)日：2010-11-30

    申请号：US11911742

    申请日：2006-03-17

    申请人： Hisaya Kato

    发明人： Hisaya Kato

    IPC分类号： B29C65/48 ,  B32B37/02 ,  A47B13/08

    CPC分类号： B27D5/003 ,  B29C63/04 ,  B29C2793/00 ,  Y10T156/1002 ,  Y10T156/1026 ,  Y10T156/1028 ,  Y10T156/1064 ,  Y10T156/1066 ,  Y10T156/1082 ,  Y10T156/12 ,  Y10T156/1702

    摘要： An apparatus for manufacturing a layered product having a curved surface part with an extremely small radius of curvature while lowering the rate of occurrence a defective product is provided. The manufacturing apparatus is for a layered product in which a decorative material is laminated on a surface and side of a base material, and includes a cutting unit for forming a first cut portion at the corner of the base material and forming a second cut portion having an arc-shaped portion at a portion of a rear surface side of the decorative material opposing to the first cutout part and a bending member for bending the decorative material at the circular arc-like part of the second cutout part.

    摘要翻译： 一种用于制造具有曲率半径小的曲面部分的层叠体的设备，同时降低了产生缺陷产物的发生率。 该制造装置用于层压产品，其中装饰材料层压在基材的表面和侧面上，并且包括切割单元，用于在基材的角部处形成第一切割部分，并形成第二切割部分，该第二切割部分具有 与第一切口部相对的装饰材料的背面侧的部分的弧形部分和用于在第二切口部分的圆弧状部分弯曲装饰材料的弯曲部件。

    Synchronization detection apparatus
    5.
    发明授权
    Synchronization detection apparatus 失效
    同步检测装置

    公开(公告)号：US07133481B2

    公开(公告)日：2006-11-07

    申请号：US10311638

    申请日：2002-04-05

    申请人： Hiroshi Azakami ,  Takaaki Konishi ,  Hisaya Kato ,  Naoya Tokunaga ,  Kazuaki Suzuki ,  Kazuya Ueda

    发明人： Hiroshi Azakami ,  Takaaki Konishi ,  Hisaya Kato ,  Naoya Tokunaga ,  Kazuaki Suzuki ,  Kazuya Ueda

    IPC分类号： H04L7/00

    CPC分类号： H04N5/211 ,  H04H40/18 ,  H04L7/042 ,  H04L7/06 ,  H04L27/02 ,  H04N5/08

    摘要： An input signal DT contains a segment synchronization signal compliant with the ATSC standard. A clock multiplication section 111 multiplies a clock CK. A switchable sampling section 112 selects a sample point from among a plurality of timing points that are defined by the multiplied clock, and samples the input signal DT at the selected sample point. Moreover, the switchable sampling section 112 switches sample points from one to another in a synchronization-unestablished state. Once the segment synchronization is established, a synchronization detection device may maintain a synchronization-established state until the field synchronization detection fails, or the synchronization detection device may output a synchronization detection signal after shifting it in the time direction based on a bit error rate RT of the input signal.

    摘要翻译： 输入信号DT包含符合ATSC标准的片段同步信号。 时钟倍增部分111将时钟CK相乘。 可切换取样部112从由倍增时钟定义的多个定时点中选择采样点，并对选择的采样点对输入信号DT进行采样。 此外，可切换采样部112在同步未建立状态下将采样点从一个切换到另一个。 一旦段同步建立，同步检测装置可以保持同步建立状态，直到现场同步检测失败，或者同步检测装置可以在基于位错误率RT在时间方向上移动同步检测信号之后输出同步检测信号 的输入信号。

    Laminated Body, Device and Method for Manufacturing the Same, and Cutter Used for Manufacturing the Same
    8.
    发明申请
    Laminated Body, Device and Method for Manufacturing the Same, and Cutter Used for Manufacturing the Same 有权
    层压体，其制造方法及其制造方法

    公开(公告)号：US20080216945A1

    公开(公告)日：2008-09-11

    申请号：US11911742

    申请日：2006-03-17

    申请人： Hisaya Kato

    发明人： Hisaya Kato

    IPC分类号： B29C65/00

    CPC分类号： B27D5/003 ,  B29C63/04 ,  B29C2793/00 ,  Y10T156/1002 ,  Y10T156/1026 ,  Y10T156/1028 ,  Y10T156/1064 ,  Y10T156/1066 ,  Y10T156/1082 ,  Y10T156/12 ,  Y10T156/1702

    摘要： An apparatus for manufacturing a layered product having a curved surface part with an extremely small radius of curvature while lowering the rate of occurrence a defective product is provided. The manufacturing apparatus is for a layered product in which a decorative material is laminated on a surface and side of a base material, and includes a cutting unit for forming a first cut portion at the corner of the base material and forming a second cut portion having an arc-shaped portion at a portion of a rear surface side of the decorative material opposing to the first cutout part and a bending member for bending the decorative material at the circular arc-like part of the second cutout part.

    摘要翻译： 一种用于制造具有曲率半径小的曲面部分的层叠体的设备，同时降低了产生缺陷产物的发生率。 该制造装置用于层压产品，其中装饰材料层压在基材的表面和侧面上，并且包括切割单元，用于在基材的角部处形成第一切割部分，并形成第二切割部分，该第二切割部分具有 与第一切口部相对的装饰材料的背面侧的部分的弧形部分和用于在第二切口部分的圆弧状部分弯曲装饰材料的弯曲部件。

    Digital demodulation device and synchronization detecting method
    9.
    发明授权
    Digital demodulation device and synchronization detecting method 有权
    数字解调装置和同步检测方法

    公开(公告)号：US07333576B2

    公开(公告)日：2008-02-19

    申请号：US10342218

    申请日：2003-01-15

    申请人： Toshiyuki Satomi ,  Naoya Tokunaga ,  Takaaki Konishi ,  Hisaya Kato

    发明人： Toshiyuki Satomi ,  Naoya Tokunaga ,  Takaaki Konishi ,  Hisaya Kato

    IPC分类号： H04B1/10 ,  H03H7/30 ,  H03H7/40 ,  H04L7/00 ,  H04N5/04

    CPC分类号： H04N5/455 ,  H04L7/06 ,  H04N5/211 ,  H04N5/4401 ,  H04N21/4382

    摘要： A synchronization error occurs when a DTV signal is distorted on a transmission path and this deteriorates demodulation capability. The digital demodulation device and the synchronization detecting method of the invention can correct the synchronization position when determining that a synchronization error has occurred. A controller receives a center tap coefficient, for example, from a waveform equalizer and compares the coefficient with a given center tap coefficient threshold. If the coefficient is smaller than the threshold, the controller determines that a synchronization detector has made a synchronization error and outputs a control signal. The synchronization detector receiving the control signal re-detects a sync signal included in a received signal, to detect a new correct sync signal and thus correct the synchronization error.

    摘要翻译： 当DTV信号在传输路径上失真时，发生同步错误，并且这会降低解调能力。 本发明的数字解调装置和同步检测方法可以在确定发生同步错误时校正同步位置。 控制器例如从波形均衡器接收中心抽头系数，并将系数与给定中心抽头系数阈值进行比较。 如果系数小于阈值，则控制器确定同步检测器已经做出同步误差并输出控制信号。 接收控制信号的同步检测器重新检测包含在接收信号中的同步信号，以检测新的正确同步信号，从而校正同步误差。

    Clock recovery circuit
    10.
    发明授权
    Clock recovery circuit 有权
    时钟恢复电路

    公开(公告)号：US06914945B2

    公开(公告)日：2005-07-05

    申请号：US09883174

    申请日：2001-06-19

    申请人： Hisaya Kato ,  Ippei Kanno ,  Hiroshi Azakami

    发明人： Hisaya Kato ,  Ippei Kanno ,  Hiroshi Azakami

    IPC分类号： H04N5/06 ,  H04J3/00 ,  H04L7/00 ,  H04L7/027 ,  H04L27/06 ,  H04N5/455 ,  H04N19/00 ,  H04N19/80 ,  H04L27/16

    CPC分类号： H04L7/027 ,  H04L7/0008

    摘要： In a clock recovery circuit for DTV using a VSB modulation method, if the frequency of the symbol clock is fs, since the frequency difference between the fs/2 component signal of the VSB signal and the pilot signal is constant at fs/2, it is possible accurately to detect the phase error from their differential signal. Furthermore there is no distortion of the clock signal frequency of the VSB signal, even when the symbol data is distorted by multi-pass distortion or the like, since clock signal regeneration is performed by frequency domain processing. By employing this type of principle and performing phase error detection for each symbol at a time, it is possible to ensure a high speed tracking performance for clock signal regeneration.

    摘要翻译： 在使用VSB调制方法的DTV的时钟恢复电路中，如果符号时钟的频率为fs，则由于VSB信号的fs / 2分量信号与导频信号之间的频率差在fs / 2是恒定的，所以 可以准确地从其差分信号中检测相位误差。 此外，即使当通过频域处理执行时钟信号再生时，即使当多通道失真等使码元数据失真时，也不会产生VSB信号的时钟信号频率的失真。 通过采用这种原理并一次执行每个符号的相位误差检测，可以确保用于时钟信号再生的高速跟踪性能。