公开(公告)号：US20120200777A1

公开(公告)日：2012-08-09

申请号：US13366898

申请日：2012-02-06

Applicant: Kouichi OOGA

Inventor： Kouichi OOGA

IPC: H04N5/14

CPC classification number: H04N5/21 ,  G09G5/003 ,  G09G2310/06 ,  G09G2330/06 ,  G09G2370/14

Abstract: There is provided a video signal processing method for performing predetermined signal processing on an input video signal to transmit an output video signal in a form of a specified transmission format through a video signal line including invalid bit polarity setting processing to be performed by an invalid bit polarity setting unit, wherein, when there exists an invalid bit having no data corresponding to data making up the input video signal in the specified transmission format of the output video signal, to count the number of low and high levels of gray-level data of the input video signal to compare a numerical size between the number of low levels and the number of high levels for judgment and to set a polarity of the invalid bit based on the judgment result.

Abstract translation: 提供了一种用于对输入视频信号执行预定信号处理的视频信号处理方法，以通过包括由无效位执行的无效位极性设置处理的视频信号线以指定传输格式的形式发送输出视频信号 极性设定单元，其中当存在与输出视频信号的指定传输格式相对应的数据不对应于输入视频信号的数据的无效位时，计数低电平和高电平的灰度数据的数量 输入视频信号，用于比较低电平数量与用于判断的高电平数量之间的数字大小，并根据判断结果设置无效位的极性。

公开(公告)号：US20120068977A1

公开(公告)日：2012-03-22

申请号：US13233222

申请日：2011-09-15

Applicant: Kouichi OOGA

Inventor： Kouichi OOGA

IPC: G06F3/038

CPC classification number: G09G3/3688 ,  G09G3/3614 ,  G09G2330/06

Abstract: An image display device and a transmission signal control method to be used in same and more particularly to the image display device and the transmission signal control method that can be suitably used when transmission wirings for data signal based on a video signal become complicated due to configurations of a large-sized and high-definition image display device.

Abstract translation: 一种图像显示装置和传输信号控制方法，更具体地涉及当由于配置而导致基于视频信号的数据信号的传输配线变得复杂时可适当使用的图像显示装置和传输信号控制方法 的大型和高清晰度图像显示装置。

公开(公告)号：US20110043512A1

公开(公告)日：2011-02-24

申请号：US12862188

申请日：2010-08-24

Applicant: Kouichi OOGA

Inventor： Kouichi OOGA

IPC: G09G5/00

CPC classification number: G09G3/3688 ,  G09G2320/0209

Abstract: The degree of an influence from wiring crosstalk between signal lines of a data signal transmission line (video signal line) is decided on the basis of an input signal generated in display controlling unit (a timing controller) at a predetermined timing (at each frame period, at each clock pulse period, or at each horizontal period) and, based on a result of the decision, the voltage amplitude of a data signal is adjusted so that it may exceed an input amplitude specification value for data line driving circuits (data drivers) by a predetermined value.

Abstract translation: 基于在预定定时（在每个帧周期（在每个帧周期））在显示控制单元（定时控制器）中产生的输入信号来决定数据信号传输线（视频信号线）的信号线之间的布线串扰的影响程度 ，在每个时钟脉冲周期或每个水平周期），并且基于该决定的结果，调整数据信号的电压幅度，使得其可能超过用于数据线驱动电路（数据驱动器）的输入幅度指定值 ）预定值。

公开(公告)号：US20100231559A1

公开(公告)日：2010-09-16

申请号：US12721264

申请日：2010-03-10

Applicant: Kouichi OOGA

Inventor： Kouichi OOGA

IPC: G09G5/00

CPC classification number: G09G5/12 ,  G09G3/20 ,  G09G3/3614 ,  G09G3/3648 ,  G09G2300/08 ,  G09G2310/08 ,  G09G2330/06

Abstract: A liquid crystal device is provided which is capable of being free from degradation of signal receiving sensitivity and/or malfunction without performing thinning-out and complementing on video signals of an electronic device having an embedded peripheral circuit to receive and transmit data. A stop period during which outputting of horizontal synchronizing signal made up of a video signal strobe signal STB and vertical drive clock signal VCK is stopped at least one time or more and for two horizontal periods or more during a display period in one vertical period is set by a control device (for example, timing controller). In this horizontal synchronizing stop period setting mode processing, a first signal (for example, status signal) indicating that the outputting of the horizontal synchronizing signal is in a stop state is transmitted to an electronic circuit (for example, peripheral circuit).

Abstract translation: 提供一种液晶装置，其能够不受信号接收灵敏度和/或故障的影响，而不会对具有嵌入式外围电路的电子设备的视频信号进行稀疏化和补充，以接收和发送数据。 设定在视频信号选通信号STB和垂直驱动时钟信号VCK构成的水平同步信号的输出至少一次以上并在一个垂直周期的显示期间停止两个水平周期以上的停止期间 通过控制装置（例如，时序控制器）。 在该水平同步停止期间设定模式处理中，向电子电路（例如外围电路）发送表示水平同步信号的输出处于停止状态的第一信号（例如，状态信号）。

公开(公告)号：US20110074377A1

公开(公告)日：2011-03-31

申请号：US12891434

申请日：2010-09-27

Applicant: Kouichi OOGA

Inventor： Kouichi OOGA

IPC: G05F5/00 ,  H03H1/00

CPC classification number: H03K17/284 ,  H03K5/13 ,  H03K2005/00156

Abstract: To provide a time constant circuit and the like capable of acquiring a characteristic of an output voltage that attenuates gradually after attenuating steeply, compared to a characteristic that attenuates monotonously. The time constant circuit includes: a series/parallel circuit formed by serially connecting a plurality of parallel circuits each formed with a resistance element and a capacitance element between a first terminal and a second terminal; and a voltage-dividing resistance element connected between a third terminal connected to the second terminal and a fourth terminal. A first parallel circuit is formed with a first resistance element and a first capacitance element, a second parallel circuit with a second resistance element and a second capacitance element, and an n-th parallel circuit with an n-th resistance element and an n-th capacitance element. Note that “n” is the number of the parallel circuits and it is an integer of 2 or larger.

Abstract translation: 为了提供一种时间常数电路等，与能够单调衰减的特性相比，能够获得与陡峭衰减后逐渐衰减的输出电压的特性。 该时间常数电路包括：串联/并联电路，其通过串联连接多个并联电路，每个并联电路各自形成有电阻元件和第一端子与第二端子之间的电容元件; 以及连接在与第二端子连接的第三端子与第四端子之间的分压电阻元件。 第一并联电路形成有第一电阻元件和第一电容元件，具有第二电阻元件的第二并联电路和第二电容元件，以及具有第n电阻元件和第n电容元件的第n并联电路， 电容元件。 注意，“n”是并联电路的数量，它是2或更大的整数。

公开(公告)号：US20080238844A1

公开(公告)日：2008-10-02

申请号：US12044381

申请日：2008-03-07

Applicant: Takaaki KAKIUCHI ,  Kouichi OOGA

Inventor： Takaaki KAKIUCHI ,  Kouichi OOGA

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3611 ,  G09G2310/08 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2330/06 ,  G09G2370/08

Abstract: A liquid crystal driver circuit includes a timing controller emitting at least two control signals therefrom, and at least two gate drivers receiving the control signals from the timing controller. The control signals are controlled such that signal levels thereof are not simultaneously varied.

Abstract translation: 液晶驱动器电路包括从其发射至少两个控制信号的定时控制器，以及从定时控制器接收控制信号的至少两个栅极驱动器。 控制信号被控制，使得其信号电平不同时变化。