Row hammer refresh command
    1.
    发明授权
    Row hammer refresh command 有权
    行锤刷新命令

    公开(公告)号:US09117544B2

    公开(公告)日:2015-08-25

    申请号:US14068677

    申请日:2013-10-31

    IPC分类号: G06F13/10 G11C11/406 G11C7/02

    摘要: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

    摘要翻译: 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值(也称为“锤击”或“行锤事件”)中重复访问时,物理上相邻的行(“受害者”行)可能会遭遇数据损坏。 存储器控制器接收行敲击事件的指示,识别与行锤事件相关联的行,并且将一个或多个命令发送到存储器设备,以使存储器设备执行将刷新受害者行的目标刷新。

    METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM
    2.
    发明申请
    METHOD AND APPARATUS FOR DYNAMICALLY ADJUSTING VOLTAGE REFERENCE TO OPTIMIZE AN I/O SYSTEM 有权
    用于动态调整电压参考以优化I / O系统的方法和装置

    公开(公告)号:US20110141827A1

    公开(公告)日:2011-06-16

    申请号:US12638887

    申请日:2009-12-15

    IPC分类号: G11C5/14

    摘要: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

    摘要翻译: 这里描述了一种用于动态调整电压参考电平以便优化I / O系统以实现某一性能度量的装置。 该装置包括:电压基准发生器,用于产生电压基准; 以及与电压参考发生器耦合的动态电压参考控制单元,以响应于事件来动态地调整电压参考电平。 该装置用于执行该方法,包括:产生用于输入/输出(I / O)系统的电压基准; 确定电压基准的最坏情况电压电平; 基于确定最坏情况电压电平,通过动态电压基准控制单元动态调整电压参考电平; 以及基于动态调整的电压参考电平计算不对称眼睛的中心。

    Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system
    3.
    发明授权
    Method and apparatus for dynamically adjusting voltage reference to optimize an I/O system 有权
    用于动态调整电压参考以优化I / O系统的方法和装置

    公开(公告)号:US08582374B2

    公开(公告)日:2013-11-12

    申请号:US12638887

    申请日:2009-12-15

    IPC分类号: G11C5/14

    摘要: Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

    摘要翻译: 这里描述了一种用于动态调整电压参考电平以便优化I / O系统以实现某一性能度量的装置。 该装置包括:电压基准发生器,用于产生电压基准; 以及与电压参考发生器耦合的动态电压参考控制单元,以响应于事件来动态地调整电压参考电平。 该装置用于执行该方法,包括:产生用于输入/输出(I / O)系统的电压基准; 确定电压基准的最坏情况电压电平; 基于确定最坏情况电压电平,通过动态电压基准控制单元动态调整电压参考电平; 以及基于动态调整的电压参考电平计算不对称眼睛的中心。

    Common analog interface for multiple processor cores
    4.
    发明授权
    Common analog interface for multiple processor cores 失效
    多个处理器内核的通用模拟接口

    公开(公告)号:US07647476B2

    公开(公告)日:2010-01-12

    申请号:US11374708

    申请日:2006-03-14

    IPC分类号: G06F7/38 G06F13/14 G11C7/10

    CPC分类号: G06F15/7832

    摘要: In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括具有多个处理器核以执行指令的处理器,其中每个核包括专用数字接口电路。 处理器还包括经由数字接口电路耦合到核的模拟接口。 模拟接口可用于在包括核心的包和诸如耦合到其之间的共享总线的互连之间传送业务。 描述和要求保护其他实施例。

    Common analog interface for multiple processor cores
    5.
    发明申请
    Common analog interface for multiple processor cores 失效
    多个处理器内核的通用模拟接口

    公开(公告)号:US20070220233A1

    公开(公告)日:2007-09-20

    申请号:US11374708

    申请日:2006-03-14

    IPC分类号: G06F15/00

    CPC分类号: G06F15/7832

    摘要: In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.

    摘要翻译: 在一个实施例中,本发明包括具有多个处理器核以执行指令的处理器,其中每个核包括专用数字接口电路。 处理器还包括经由数字接口电路耦合到核的模拟接口。 模拟接口可用于在包括核心的包和诸如耦合到其之间的共享总线的互连之间传送业务。 描述和要求保护其他实施例。