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    Common analog interface for multiple processor cores
    1.
    发明申请
    Common analog interface for multiple processor cores 失效
    多个处理器内核的通用模拟接口

    公开(公告)号：US20070220233A1

    公开(公告)日：2007-09-20

    申请号：US11374708

    申请日：2006-03-14

    申请人： Christopher Mozak ,  Jeffrey Gilbert ,  Ganapati Srinivasa

    发明人： Christopher Mozak ,  Jeffrey Gilbert ,  Ganapati Srinivasa

    IPC分类号： G06F15/00

    CPC分类号： G06F15/7832

    摘要： In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.

    摘要翻译： 在一个实施例中，本发明包括具有多个处理器核以执行指令的处理器，其中每个核包括专用数字接口电路。 处理器还包括经由数字接口电路耦合到核的模拟接口。 模拟接口可用于在包括核心的包和诸如耦合到其之间的共享总线的互连之间传送业务。 描述和要求保护其他实施例。

    EXCHANGING INFORMATION BETWEEN COMPONENTS COUPLED WITH AN A I2C BUS VIA SEPARATE BANKS
    3.
    发明申请
    EXCHANGING INFORMATION BETWEEN COMPONENTS COUPLED WITH AN A I2C BUS VIA SEPARATE BANKS 审中-公开
    通过独立银行与I2C总线相连的组件之间的交换信息

    公开(公告)号：US20090327572A1

    公开(公告)日：2009-12-31

    申请号：US12164757

    申请日：2008-06-30

    申请人： In Sung Cho ,  Kumar Mahesh ,  Prakash Kamath ,  Jeffrey Gilbert ,  Rob Frizzell

    发明人： In Sung Cho ,  Kumar Mahesh ,  Prakash Kamath ,  Jeffrey Gilbert ,  Rob Frizzell

    IPC分类号： G06F12/06

    CPC分类号： G06F13/4291

    摘要： A method and apparatus for exchanging information between components coupled with an a I2C bus via separate banks. In one embodiment, the apparatus is for use in a wireless communication system for communicating with a wireless network and comprises a host processor having an I2C interface, a transceiver having an I2C interface, a physical interface coupling the host processor and the transceiver, the physical interface having an I2C bus coupled to the I2C interface of both the host processor and the transceiver and multiple separate banks of memory accessible by the host processor and the transceiver to exchange information between the host processor and the transceiver, where the host processor and the transceiver access the plurality of banks of memory via their respective I2C interfaces.

    摘要翻译： 一种用于通过单独的银行在与I2C总线耦合的组件之间交换信息的方法和装置。 在一个实施例中，该装置用于与无线网络通信的无线通信系统，并且包括具有I2C接口的主处理器，具有I2C接口的收发器，耦合主机处理器和收发器的物理接口，物理 接口具有耦合到主处理器和收发器的I2C接口的I2C总线以及由主机处理器和收发器可访问的多个独立存储体，以在主处理器和收发器之间交换信息，其中主处理器和收发器 通过它们各自的I2C接口访问多个存储器组。

    DISPATCH CAPABILITY USING A SINGLE PHYSICAL INTERFACE
    4.
    发明申请
    DISPATCH CAPABILITY USING A SINGLE PHYSICAL INTERFACE 有权
    使用单个物理接口的分配能力

    公开(公告)号：US20090327544A1

    公开(公告)日：2009-12-31

    申请号：US12164907

    申请日：2008-06-30

    申请人： In Sung Cho ,  Kumar Mahesh ,  Prakash Kamath ,  Jeffrey Gilbert ,  Rob Frizzell

    发明人： In Sung Cho ,  Kumar Mahesh ,  Prakash Kamath ,  Jeffrey Gilbert ,  Rob Frizzell

    IPC分类号： G06F13/42

    CPC分类号： H04N21/43637 ,  G06F1/00 ,  G06F13/42 ,  G06F2101/00 ,  G09G2370/16 ,  H04L1/00 ,  H04L69/32

    摘要： An apparatus, system and method for performing dispatch operations using a signal physical interface are disclosed. In one embodiment, the apparatus is for use in a wireless communication system for communicating with a wireless network and comprises a host processor, a transceiver, a physical interface coupling the host processor and the transceiver, and a memory accessible by the host processor and the transceiver to exchange information between the host processor and the transceiver. The transceiver is operable to store data in the memory for the host processor to send data to the host processor using the memory and asserts a control signal to the host processor to notify the host processor that the memory contains data for the host processor, and the host processor is operable to access the memory to obtain the data thereafter. The data is associated with a remote device in the wireless network and is stored as one or more packets at a first storage location in the memory with a first identifier identifying the remote device.

    摘要翻译： 公开了一种使用信号物理接口执行调度操作的装置，系统和方法。 在一个实施例中，该装置用于与无线网络进行通信的无线通信系统，并且包括主机处理器，收发器，耦合主机处理器和收发器的物理接口以及主机处理器和 收发器在主处理器和收发器之间交换信息。 收发器可操作以将存储器中的数据存储在主机处理器中，以使用存储器向主机处理器发送数据，并向主机处理器发出控制信号，以通知主机处理器该存储器包含用于主机处理器的数据， 主机处理器可操作以访问存储器以便此后获得数据。 数据与无线网络中的远程设备相关联，并且以识别远程设备的第一标识符作为一个或多个分组存储在存储器中的第一存储位置处。

    Way hint line replacement algorithm for a snoop filter
    5.
    发明申请
    Way hint line replacement algorithm for a snoop filter 审中-公开
    用于窥探过滤器的方式提示行替换算法

    公开(公告)号：US20070233965A1

    公开(公告)日：2007-10-04

    申请号：US11395123

    申请日：2006-03-31

    申请人： Kai Cheng ,  Rob Milstrey ,  Jeffrey Gilbert ,  Liqun Cheng ,  Lily Looi ,  Faye Briggs

    发明人： Kai Cheng ,  Rob Milstrey ,  Jeffrey Gilbert ,  Liqun Cheng ,  Lily Looi ,  Faye Briggs

    IPC分类号： G06F13/28

    CPC分类号： G06F12/0831

    摘要： A system and method for maintaining data coherency in a multiprocessor environment. The system includes a snoop filter that maintains a representation of the organization and context of each last level cache on the system. The representative is updated with each request which each include a hint to the location where requested data will be stored in the last level cache.

    摘要翻译： 一种用于在多处理器环境中维护数据一致性的系统和方法。 该系统包括一个窥探过滤器，用于维护系统上每个最后一级缓存的组织和上下文的表示。 每个请求更新代表，每个请求都包含对所请求数据将存储在最后一级缓存中的位置的提示。

    System and method for identifying a retail customer's purchasing habits
    7.
    发明申请
    System and method for identifying a retail customer's purchasing habits 有权
    识别零售客户购买习惯的系统和方法

    公开(公告)号：US20050173522A1

    公开(公告)日：2005-08-11

    申请号：US10936754

    申请日：2004-09-08

    申请人： Kyle Turner ,  Kevin Morrin ,  Jeffrey Gilbert

    发明人： Kyle Turner ,  Kevin Morrin ,  Jeffrey Gilbert

    IPC分类号： G06F20060101 ,  G06K15/00 ,  G06F17/60

    CPC分类号： G07G5/00 ,  G06Q30/02 ,  G06Q30/0238 ,  G06Q30/0242 ,  G07G1/12

    摘要： A system and method for targeting marketing messages at a point-of-sale consumer by collecting current transactional receipt data, such as the time of a retail transaction, the date of the transaction, the number of items purchased the transaction, and the total dollar value of a transaction. The data collected from the receipt is then applied to one or more algorithms to determine which marketing messages are most likely to be successful. A predetermined number of marketing messages found most likely to be successful are then printed on the customer receipt in order of priority of expected effectiveness. The system is designed to be used in connection with a point-of-sale terminal without the need for additional hardware, such as a second printer, or the need to access historical customer data.

    摘要翻译： 一种系统和方法，用于通过收集当前的交易收据数据来定位销售点消费者的营销信息，例如零售交易的时间，交易的日期，交易的购买数量以及总的美元 交易价值。 然后将从收据收集的数据应用于一种或多种算法，以确定哪些营销消息最有可能成功。 然后按照预期效果的优先次序，将最可能成功的预定数量的营销消息印在客户收据上。 该系统被设计为与销售点终端相关联使用，而不需要诸如第二打印机的附加硬件，或者需要访问历史客户数据。

    Spur mitigation techniques
    9.
    发明申请
    Spur mitigation techniques 审中-公开
    刺激减轻技术

    公开(公告)号：US20050059366A1

    公开(公告)日：2005-03-17

    申请号：US10664792

    申请日：2003-09-16

    申请人： Won-Joon Choi ,  Jeffrey Gilbert ,  Yi-Hsiu Wang ,  Xiaoru Zhang

    发明人： Won-Joon Choi ,  Jeffrey Gilbert ,  Yi-Hsiu Wang ,  Xiaoru Zhang

    IPC分类号： H04L27/26 ,  H04B1/00

    CPC分类号： H04L25/0232 ,  H04L1/0045 ,  H04L27/2647

    摘要： Spurs cause significant problems with signal detecting, amplifier gain adjustment, and signal decoding. Various techniques can be used to mitigate the effects of spurs on a received signal. Generally, these techniques work by either canceling or ignoring the spurs. For example, a pilot mask can be used to ignore pilot information in one or more sub-channels. A Viterbi mask can determine the weighting given to bits in a sub-channel based on spur and data rate information. Channel interpolation can compute a pseudo channel estimate for a sub-channel known to have a spur location can be computed by interpolating the channel estimates of adjacent good sub-channels. Filtering of the received signal using a low-pass filter, a growing box filter, or a low-pass filter with self-correlation can be used to cancel a spur.

    摘要翻译： 马刺在信号检测，放大器增益调整和信号解码方面造成重大问题。 可以使用各种技术来减轻杂散对接收信号的影响。 一般来说，这些技术通过取消或忽略杂散来工作。 例如，可以使用导频掩码来忽略一个或多个子信道中的导频信息。 维特比掩码可以基于支线和数据速率信息来确定子信道中的比特的加权。 信道内插可以计算已知具有支路位置的子信道的伪信道估计，可以通过内插相邻的良好子信道的信道估计来计算。 使用低通滤波器，增长盒滤波器或具有自相关的低通滤波器对接收信号进行滤波可以用于取消杂散。