公开(公告)号：US09117544B2

公开(公告)日：2015-08-25

申请号：US14068677

申请日：2013-10-31

Applicant: Kuljit Bains ,  John Halbert ,  Christopher Mozak ,  Theodore Schoenborn ,  Zvika Greenfield

Inventor： Kuljit Bains ,  John Halbert ,  Christopher Mozak ,  Theodore Schoenborn ,  Zvika Greenfield

IPC: G06F13/10 ,  G11C11/406 ,  G11C7/02

CPC classification number: G11C11/40615 ,  G11C7/02 ,  G11C11/40611 ,  G11C11/40622

Abstract: A memory controller issues a targeted refresh command. A specific row of a memory device can be the target of repeated accesses. When the row is accessed repeatedly within a time threshold (also referred to as “hammered” or a “row hammer event”), physically adjacent row (a “victim” row) may experience data corruption. The memory controller receives an indication of a row hammer event, identifies the row associated with the row hammer event, and sends one or more commands to the memory device to cause the memory device to perform a targeted refresh that will refresh the victim row.

Abstract translation: 内存控制器发出目标刷新命令。 存储器件的特定行可以是重复访问的目标。 当行在时间阈值（也称为“锤击”或“行锤事件”）中重复访问时，物理上相邻的行（“受害者”行）可能会遭遇数据损坏。 存储器控制器接收行敲击事件的指示，识别与行锤事件相关联的行，并且将一个或多个命令发送到存储器设备，以使存储器设备执行将刷新受害者行的目标刷新。

公开(公告)号：US20150109871A1

公开(公告)日：2015-04-23

申请号：US14108830

申请日：2013-12-17

Applicant: Kuljit BAINS ,  John Halbert

Inventor： Kuljit BAINS ,  John Halbert

IPC: G11C11/4078 ,  G11C11/406

CPC classification number: G11C11/4078 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/408 ,  G11C29/50 ,  G11C29/50012 ,  G11C2029/0409

Abstract: Detection logic of a memory subsystem obtains a threshold for a memory device that indicates a number of accesses within a time window that causes risk of data corruption on a physically adjacent row. The detection logic obtains the threshold from a register that stores configuration information for the memory device, and can be a register on the memory device itself and/or can be an entry of a configuration storage device of a memory module to which the memory device belongs. The detection logic determines whether a number of accesses to it row of the memory device exceeds the threshold. In response to detecting the number of accesses exceeds the threshold, the detection logic can generate a trigger to cause the memory device to perform a refresh targeted to a physically adjacent victim row.

Abstract translation: 存储器子系统的检测逻辑获得存储器设备的阈值，该存储器设备指示在时间窗口内的数量的访问，导致物理上相邻的行上的数据损坏风险。 检测逻辑从存储器件的配置信息的寄存器获得阈值，并且可以是存储器件本身的寄存器和/或可以是存储器件所属的存储器模块的配置存储设备的条目 。 检测逻辑确定存储器件的行的访问次数是否超过阈值。 响应于检测到的访问次数超过阈值，检测逻辑可以产生触发以使存储器件执行针对物理上相邻的受害者行的刷新。

公开(公告)号：US20080056047A1

公开(公告)日：2008-03-06

申请号：US11932470

申请日：2007-10-31

Applicant: Sandeep Jain ,  Animesh Mishra ,  John Halbert

Inventor： Sandeep Jain ,  Animesh Mishra ,  John Halbert

IPC: G11C7/00

CPC classification number: G11C11/40611 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/40622

Abstract: A method, apparatus, and system to enable a partial refresh scheme for DRAM which includes specifying at least a refresh start value, or a refresh start value and a refresh end value, to reduce the number of rows that must be refreshed during a refresh cycle, thus reducing the amount of power consumed during refresh.

Abstract translation: 一种能够实现DRAM的部分刷新方案的方法，装置和系统，其包括至少指定刷新开始值或刷新开始值和刷新结束值，以减少刷新周期期间必须刷新的行数 ，从而减少刷新期间消耗的功率量。

公开(公告)号：US20070211548A1

公开(公告)日：2007-09-13

申请号：US11801909

申请日：2007-05-10

Applicant: Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

Inventor： Sandeep Jain ,  David Wyatt ,  Jun Shi ,  Animesh Mishra ,  John Halbert ,  Melik Isbara

IPC: G11C7/04

CPC classification number: G11C7/04 ,  G06F11/3037 ,  G06F11/3058 ,  G06F11/3089 ,  G11C5/04 ,  G11C5/143 ,  G11C7/1051 ,  G11C7/1063

Abstract: The temperature for multiple devices of a memory module are determined. In one example a memory module includes a printed circuit board, a plurality of memory chips on the printed circuit board, each chip containing a plurality of memory cells and a thermal sensor, and a multiplexer on the printed circuit board, independent of the memory chips, coupled to each of the thermal sensors. A current source is coupled to the multiplexer to provide a current to each one of the thermal sensors, and a voltage detector is coupled to the multiplexer to detect a voltage from each of the thermal sensors when a current is applied. A temperature circuit is coupled to the voltage detector to determine a temperature for each memory chip based on the detected voltage.

Abstract translation: 确定存储器模块的多个设备的温度。 在一个示例中，存储器模块包括印刷电路板，印刷电路板上的多个存储器芯片，每个芯片包含多个存储单元和热传感器，以及印刷电路板上的多路复用器，独立于存储器芯片 ，耦合到每个热传感器。 电流源耦合到多路复用器以向每个热传感器提供电流，并且电压检测器耦合到多路复用器以在施加电流时检测来自每个热传感器的电压。 温度电路耦合到电压检测器，以基于检测到的电压来确定每个存储器芯片的温度。

公开(公告)号：US20050144375A1

公开(公告)日：2005-06-30

申请号：US10750154

申请日：2003-12-31

Applicant: Kuljit Bains ,  John Halbert ,  Randy Osborne

Inventor： Kuljit Bains ,  John Halbert ,  Randy Osborne

IPC: G06F12/00 ,  G06F13/16

CPC classification number: G06F13/161

Abstract: Memory device having banks of memory cells organized into two groups of banks that share control circuitry and a data buffer to provide an interface to a memory bus, but which are independently operable enough to support unrelated transactions with each group, and can be used to stagger read operations with shortened burst transfers so as to minimize dead time on a memory bus.

Abstract translation: 具有存储单元组的存储器单元被组织成共享控制电路的两组存储体，以及数据缓冲器以提供与存储器总线的接口，但它们独立地可操作以足以支持与每个组的无关交易，并且可以用于交错 以缩短的突发传输进行读操作，以最大限度地减少内存总线上的死区时间。

公开(公告)号：US06530006B1

公开(公告)日：2003-03-04

申请号：US09664982

申请日：2000-09-18

Applicant: James M. Dodd ,  Michael W. Williams ,  John Halbert ,  Randy M. Bonella

Inventor： James M. Dodd ,  Michael W. Williams ,  John Halbert ,  Randy M. Bonella

IPC: G06F1200

CPC classification number: G06F13/4239

Abstract: The present invention provides a system and method for providing reliable transmission in a buffered memory system. The system includes memory devices, a memory controller, data buffers, an address/command buffer, and a clock circuit. The memory controller sends data, address information, status information and command information, to the memory devices and receives data from the memory devices. The buffers interconnect the memory devices and the memory controller. The clock circuit is embedded in the addr/cmd buffer. The clock circuit takes an input clock and outputs an output clock to the data buffers and/or the memory devices to control clock-skew to the data buffers and/or the memory devices.

Abstract translation: 本发明提供了一种用于在缓冲存储器系统中提供可靠传输的系统和方法。 该系统包括存储器件，存储器控制器，数据缓冲器，地址/命令缓冲器和时钟电路。 存储器控制器向存储器件发送数据，地址信息，状态信息和命令信息，并从存储器件接收数据。 缓冲器互连存储器件和存储器控制器。 时钟电路嵌入到addr / cmd缓冲区中。 时钟电路接收输入时钟，并将输出时钟输出到数据缓冲器和/或存储器件，以控制数据缓冲器和/或存储器件的时钟偏移。

公开(公告)号：US20130272049A1

公开(公告)日：2013-10-17

申请号：US13997148

申请日：2011-12-02

Applicant: Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

Inventor： Pete Vogt ,  Andre Schaefer ,  Warren Morrow ,  John Halbert ,  Jin Kim ,  Kenneth Shoemaker

IPC: G11C5/06 ,  H01L23/48

CPC classification number: H01L25/0657 ,  G11C5/06 ,  H01L23/481 ,  H01L24/16 ,  H01L27/108 ,  H01L27/10882 ,  H01L27/10897 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541

Abstract: Dynamic operations for operations for a stacked memory with interface providing offset interconnects. An embodiment of memory device includes a system element and a memory stack coupled with the system element, the memory stack including one or more memory die layers. Each memory die layer includes first face and a second face, the second face of each memory die layer including an interface for coupling data interface pins of the memory die layer with data interface pins of a first face of a coupled element. The interface of each memory die layer includes connections that provide an offset between each of the data interface pins of the memory die layer and a corresponding data interface pin of the data interface pins of the coupled element.

Abstract translation: 用于具有提供偏移互连的接口的堆叠存储器的操作的动态操作。 存储器件的实施例包括与系统元件耦合的系统元件和存储器堆栈，存储器堆栈包括一个或多个存储器管芯层。 每个存储器管芯层包括第一面和第二面，每个存储管芯层的第二面包括用于将存储管芯层的数据接口引脚与耦合元件的第一面的数据接口引脚耦合的接口。 每个存储器管芯层的接口包括在存储管芯层的每个数据接口引脚和耦合元件的数据接口引脚的相应数据接口引脚之间提供偏移的连接。

公开(公告)号：US20070244948A1

公开(公告)日：2007-10-18

申请号：US11392471

申请日：2006-03-28

Applicant: Kuljit Bains ,  John Halbert ,  Greg Lemos ,  Randy Osborne

Inventor： Kuljit Bains ,  John Halbert ,  Greg Lemos ,  Randy Osborne

IPC: G06F7/78

CPC classification number: G06F13/1678

Abstract: In some embodiments, data may be transferred from a first memory agent to a second memory agent in a first format having a first width, and at least a critical portion of the data maybe transferred from the second memory agent back to the first memory agent in a second format having a second width, where the critical portion is included in a first frame. The critical portion may include a cacheline mapped over a memory device rank. Other embodiments are described and claimed.

Abstract translation: 在一些实施例中，数据可以以具有第一宽度的第一格式从第一存储器传送到第二存储器代理，并且数据的至少关键部分可以从第二存储器代理返回到第一存储器 具有第二宽度的第二格式，其中临界部分包括在第一帧中。 关键部分可以包括在存储器设备等级上映射的高速缓存线。 描述和要求保护其他实施例。

公开(公告)号：US20070223264A1

公开(公告)日：2007-09-27

申请号：US11388464

申请日：2006-03-24

Applicant: Kuljit S. Bains ,  John Halbert

Inventor： Kuljit S. Bains ,  John Halbert

IPC: G11C5/06

CPC classification number: G11C8/12

Abstract: In some embodiments, a chip includes at least four groups of memory banks and at least four groups of output conductors wherein each group of output conductors corresponds to a different one of the groups of memory banks. The chip also includes circuitry to perform a read operation by providing read data from at least one of the banks of each of the groups of memory banks to its corresponding group of output conductors. Other embodiments are described.

Abstract translation: 在一些实施例中，芯片包括至少四组存储器组和至少四组输出导体，其中每组输出导体对应于存储器组组中的不同组。 芯片还包括通过将存储器组中的每一组的至少一个存储体的读取数据提供给其对应的输出导体组来执行读取操作的电路。 描述其他实施例。

公开(公告)号：US20050138267A1

公开(公告)日：2005-06-23

申请号：US10746948

申请日：2003-12-23

Applicant: Kuljit Bains ,  Robert Ellis ,  Chris Freeman ,  John Halbert ,  Michael Williams

Inventor： Kuljit Bains ,  Robert Ellis ,  Chris Freeman ,  John Halbert ,  Michael Williams

IPC: G11C5/00 ,  G11C7/10 ,  G11C7/20 ,  G06F12/16

CPC classification number: G11C7/1051 ,  G06F13/1673 ,  G06F13/1684 ,  G11C7/1078 ,  G11C7/20

Abstract: Method and apparatus for use with buffered memory modules are included among the embodiments. In exemplary systems, a serial presence detect function is included within a memory module buffer instead of being provided by a separate EEPROM device mounted on the memory module. Various embodiments thus can provide cost savings, chip placement and signal routing simplification, and can in some circumstances save pins on the module. Other embodiments are described and claimed.

Abstract translation: 在实施例中包括用于缓冲存储器模块的方法和装置。 在示例性系统中，串行存在检测功能被包括在存储器模块缓冲器内，而不是由安装在存储器模块上的单独的EEPROM器件提供。 因此，各种实施例可以提供成本节省，芯片放置和信号路由简化，并且在某些情况下可以在模块上保存引脚。 描述和要求保护其他实施例。