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公开(公告)号：US20070220233A1
公开(公告)日：2007-09-20
申请号：US11374708
申请日：2006-03-14
IPC分类号： G06F15/00
CPC分类号： G06F15/7832
摘要： In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有多个处理器核以执行指令的处理器，其中每个核包括专用数字接口电路。 处理器还包括经由数字接口电路耦合到核的模拟接口。 模拟接口可用于在包括核心的包和诸如耦合到其之间的共享总线的互连之间传送业务。 描述和要求保护其他实施例。
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公开(公告)号：US07647476B2
公开(公告)日：2010-01-12
申请号：US11374708
申请日：2006-03-14
CPC分类号： G06F15/7832
摘要： In one embodiment, the present invention includes a processor having multiple processor cores to execute instructions, with each of the cores including dedicated digital interface circuitry. The processor further includes an analog interface coupled to the cores via the digital interface circuitry. The analog interface may be used to communicate traffic between a package including the cores and an interconnect such as a shared bus coupled thereto. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有多个处理器核以执行指令的处理器，其中每个核包括专用数字接口电路。 处理器还包括经由数字接口电路耦合到核的模拟接口。 模拟接口可用于在包括核心的包和诸如耦合到其之间的共享总线的互连之间传送业务。 描述和要求保护其他实施例。
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3.发明授权Dynamically adjusting power of non-core processor circuitry including buffer circuitry 有权动态调整包括缓冲电路在内的非核心处理器电路的功率公开(公告)号：US08914650B2
公开(公告)日：2014-12-16
申请号：US13247594
申请日：2011-09-28
申请人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
发明人： Krishnakanth Sistla , Dean Mulla , Vivek Garg , Mark Rowland , Suresh Doraiswamy , Ganapati Srinivasa , Jeffrey D. Gilbert
CPC分类号： G06F1/324 , G06F13/4022 , Y02D10/126
摘要： In one embodiment, the present invention includes a multicore processor having a variable frequency domain including a plurality of cores and at least a portion of non-core circuitry of the processor. This non-core portion can include a cache memory, a cache controller, and an interconnect structure. In addition to this variable frequency domain, the processor can further have a fixed frequency domain including a power control unit (PCU). This unit may be configured to cause a frequency change to the variable frequency domain without draining the non-core portion of pending transactions. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有包括多个核心的可变频域和该处理器的至少一部分非核心电路的多核处理器。 该非核心部分可以包括高速缓冲存储器，高速缓存控制器和互连结构。 除了该可变频域之外，处理器还可以具有包括功率控制单元（PCU）的固定频域。 该单元可以被配置为引起对可变频域的频率改变，而不会排除待处理事务的非核心部分。 描述和要求保护其他实施例。
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公开(公告)号：US07277992B2
公开(公告)日：2007-10-02
申请号：US11087916
申请日：2005-03-22
IPC分类号： G06F12/00
CPC分类号： G06F12/128 , G06F12/0811 , G06F12/0831
摘要： A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.
摘要翻译： 一种用于智能驱逐包含缓存架构内的高速缓存行的技术。 更具体地，本发明的实施例涉及一种基于在高级缓存和较低级别高速缓存之间生成的高速缓存一致性流量来驱逐包容性高速缓存层级内的高速缓存行的技术。
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5.发明申请公开(公告)号：US20070094453A1
公开(公告)日：2007-04-26
申请号：US11256536
申请日：2005-10-21
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/383 , G06F12/0862 , G06F2212/502
摘要： A discussion of a dynamic configuration for a prefetcher is proposed. For example, a thread specific latency metric is calculated and provides dynamic feedback to the software on a per thread basis via the configuration and status registers. Likewise, the software can optionally use the information from the registers to dynamically configure the prefetching behavior and allows the software to be able to both query the performance and configure the prefetcher.
摘要翻译： 提出了对预取器的动态配置的讨论。 例如，计算线程特定的延迟度量，并通过配置和状态寄存器在每个线程的基础上向软件提供动态反馈。 同样，软件可以选择使用来自寄存器的信息来动态地配置预取行为，并允许软件能够查询性能并配置预取器。
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公开(公告)号：US20060218352A1
公开(公告)日：2006-09-28
申请号：US11087916
申请日：2005-03-22
CPC分类号： G06F12/128 , G06F12/0811 , G06F12/0831
摘要： A technique for intelligently evicting cache lines within an inclusive cache architecture. More particularly, embodiments of the invention relate to a technique to evict cache lines within an inclusive cache hierarchy based on the cache coherency traffic generated between an upper level cache and lower level caches.
摘要翻译： 一种用于智能驱逐包含缓存架构内的高速缓存行的技术。 更具体地，本发明的实施例涉及一种基于在高级缓存和较低级别高速缓存之间生成的高速缓存一致性流量来驱逐包容性高速缓存层级内的高速缓存行的技术。
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公开(公告)号：US08412970B2
公开(公告)日：2013-04-02
申请号：US13329700
申请日：2011-12-19
IPC分类号： G06F1/00
CPC分类号： G06F1/3243 , G06F1/206 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3275 , G06F1/3287 , G06F12/0811 , G06F15/80 , G06F2212/283 , G11C7/1072 , G11C7/1075 , Y02D10/16
摘要： A method and apparatus to monitor architecture events is disclosed. The architecture events are linked together via a push bus mechanism with each architectural event having a designated time slot. There is at least one branch of the push bus in each core. Each branch of the push bus may monitor one core with all the architectural events. All the data collected from the events by the push bus is then sent to a power control unit.
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公开(公告)号：US20120179878A1
公开(公告)日：2012-07-12
申请号：US13422806
申请日：2012-03-16
IPC分类号： G06F12/08
CPC分类号： G06F15/17337 , G06F12/0817 , G06F12/0831
摘要： In one embodiment, link logic of a multi-chip processor (MCP) formed using multiple processors may interface with a first point-to-point (PtP) link coupled between the MCP and an off-package agent and another PtP link coupled between first and second processors of the MCP, where the on-package PtP link operates at a greater bandwidth than the first PtP link. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，使用多个处理器形成的多芯片处理器（MCP）的链路逻辑可以与耦合在MCP和非封装代理之间的第一点对点（PtP）链路以及耦合在第一 和MCP的第二个处理器，其中的封装PtP链路以比第一个PtP链路更大的带宽工作。 描述和要求保护其他实施例。
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公开(公告)号：US07353338B2
公开(公告)日：2008-04-01
申请号：US11302646
申请日：2005-12-14
申请人： Yen-Cheng Liu , Krishnakanth Sistla , George Cai , Ganapati Srinivasa , Geeyarpuram Santhanakrishnan
发明人： Yen-Cheng Liu , Krishnakanth Sistla , George Cai , Ganapati Srinivasa , Geeyarpuram Santhanakrishnan
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F9/5016 , G06F9/544 , G06F2209/504 , G06F2212/271 , Y02D10/22
摘要： Methods and apparatus to manage credits in a computing system with multiple banks of shared cache are described. In one embodiment, a credit request from a processor core is translated into a physical credit that corresponds to one of the multiple banks of shared cache.
摘要翻译： 描述了在具有多个共享缓存组的计算系统中管理信用的方法和装置。 在一个实施例中，来自处理器核心的信用请求被转换成对应于多个共享高速缓冲存储区之一的物理信用。
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10.发明申请MIGRATING TASKS BETWEEN ASYMMETRIC COMPUTING ELEMENTS OF A MULTI-CORE PROCESSOR 审中-公开多核处理器的不对称计算元素之间的迁移任务公开(公告)号：US20140129808A1
公开(公告)日：2014-05-08
申请号：US13994142
申请日：2012-04-27
申请人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
发明人： Alon Naveh , Yuval Yosef , Eliezer Weissmann , Anil Aggarwal , Efraim Rotem , Avi Mendelson , Ronny Ronen , Boris Ginzburg , Michael Mishaeli , Scott D. Hahn , David A. Koufaty , Ganapati Srinivasa , Guy Therien
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/4856 , G06F9/5094 , G06F2209/5018 , Y02D10/22 , Y02D10/24 , Y02D10/32
摘要： In one embodiment, the present invention includes a multicore processor having first and second cores to independently execute instructions, the first core visible to an operating system (OS) and the second core transparent to the OS and heterogeneous from the first core. A task controller, which may be included in or coupled to the multicore processor, can cause dynamic migration of a first process scheduled by the OS to the first core to the second core transparently to the OS. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有第一和第二核心以独立执行指令的多核处理器，操作系统（OS）可见的第一核心和对OS可透明的第二核心，并且与第一核心不同。 可以包括在多核处理器中或耦合到多核处理器的任务控制器可以使由OS所安排的第一进程到OS的第一核心到第二核心的动态迁移到第二核心。 描述和要求保护其他实施例。
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