公开(公告)号：US08868992B2

公开(公告)日：2014-10-21

申请号：US12651252

申请日：2009-12-31

申请人： Bryan L. Spry ,  Theodore Z. Schoenborn ,  Philip Abraham ,  Christopher P. Mozak ,  David G. Ellis ,  Jay J. Nejedlo ,  Bruce Querbach ,  Zvika Greenfield ,  Rony Ghattas ,  Jayasekhar Tholiyil ,  Charles D. Lucas ,  Christopher E. Yunker

发明人： Bryan L. Spry ,  Theodore Z. Schoenborn ,  Philip Abraham ,  Christopher P. Mozak ,  David G. Ellis ,  Jay J. Nejedlo ,  Bruce Querbach ,  Zvika Greenfield ,  Rony Ghattas ,  Jayasekhar Tholiyil ,  Charles D. Lucas ,  Christopher E. Yunker

IPC分类号： G06F11/00 ,  G11C29/08

CPC分类号： G11C29/08 ,  G11C29/10 ,  G11C29/44

摘要： REUT (Robust Electrical Unified Testing) for memory links is introduced which speeds testing, tool development, and debug. In addition it provides training hooks that have enough performance to be used by BIOS to train parameters and conditions that have not been possible with past implementations. Address pattern generation circuitry is also disclosed.

摘要翻译： 引入了用于存储器链接的REUT（鲁棒电气统一测试），可以加速测试，开发和调试。 此外，它还提供了具有足够性能的训练钩子，以供BIOS使用，以训练过去实施中不可能的参数和条件。 还公开了地址图案生成电路。

公开(公告)号：US09734116B2

公开(公告)日：2017-08-15

申请号：US14658021

申请日：2015-03-13

申请人： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

发明人： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

IPC分类号： G06F13/14 ,  G06F13/42 ,  G06F13/12

CPC分类号： G06F13/4221 ,  G06F13/122 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

摘要： Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.

公开(公告)号：US20150269108A1

公开(公告)日：2015-09-24

申请号：US14658021

申请日：2015-03-13

申请人： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

发明人： Bryan L. Spry ,  Marcus W. Song ,  Deepak M. Rangaraj ,  Avinash N. Ananthakrishnan ,  Robert J. Hayes ,  Aimee D. Wood ,  Adam E. Letendre ,  Brent R. Boswell

IPC分类号： G06F13/42

CPC分类号： G06F13/4221 ,  G06F13/122 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

摘要： Techniques and mechanisms for configuring an integrated circuit (IC) chip to implement a protocol stack. In an embodiment, a transaction layer of the IC chip is operable to exchange with a link layer of the IC chip transaction layer packets (TLPs) having a format compatible with one defined in a Peripheral Component Interconnect Express™ (PCIe™) specification. Configuration circuitry of the IC chip provides for configuration of a first protocol stack including the transaction layer, circuitry of the link layer and a first physical layer of the IC chip. The configuration circuitry further provides for an alternative configuration of a second protocol stack including the transaction layer, circuitry of the link layer and a second physical layer of the IC chip. In another embodiment, the first protocol stack supports single-ended signaling to communicate TLP information, whereas the second protocol stack supports differential signaling to communicate TLP information.

摘要翻译： 用于配置集成电路（IC）芯片以实现协议栈的技术和机制。 在一个实施例中，IC芯片的事务层可操作以与具有与外围组件互连Express（TM TM）规范中定义的格式兼容的格式的IC芯片事务层分组（TLP）的链路层进行交换。 IC芯片的配置电路提供包括交易层，链路层的电路和IC芯片的第一物理层的第一协议栈的配置。 配置电路还提供包括交易层，链路层的电路和IC芯片的第二物理层的第二协议栈的备选配置。 在另一实施例中，第一协议栈支持单端信令来传送TLP信息，而第二协议栈支持差分信令来传送TLP信息。

公开(公告)号：US20140119137A1

公开(公告)日：2014-05-01

申请号：US14150334

申请日：2014-01-08

申请人： Christopher P. MOZAK ,  Kevin B. MOORE ,  John V. LOVELACE ,  Theodore Z. SCHOENBORN ,  Bryan L. SPRY ,  Christopher E. YUNKER

发明人： Christopher P. MOZAK ,  Kevin B. MOORE ,  John V. LOVELACE ,  Theodore Z. SCHOENBORN ,  Bryan L. SPRY ,  Christopher E. YUNKER

IPC分类号： G11C5/14 ,  G11C11/4074

CPC分类号： G11C11/4091 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4099

摘要： Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

摘要翻译： 这里描述了一种用于动态调整电压参考电平以便优化I / O系统以实现某一性能度量的装置。 该装置包括：电压基准发生器，用于产生电压基准; 以及与电压参考发生器耦合的动态电压参考控制单元，以响应于事件来动态地调整电压参考电平。 该装置用于执行该方法，包括：产生用于输入/输出（I / O）系统的电压基准; 确定电压基准的最坏情况电压电平; 基于确定最坏情况电压电平，通过动态电压基准控制单元动态调整电压参考电平; 以及基于动态调整的电压参考电平计算不对称眼睛的中心。

公开(公告)号：US20140063982A1

公开(公告)日：2014-03-06

申请号：US14072540

申请日：2013-11-05

申请人： Christopher P. MOZAK ,  Kevin B. MOORE ,  John V. LOVELACE ,  Theodore Z. SCHOENBORN ,  Bryan L. SPRY ,  Christopher E. YUNKER

发明人： Christopher P. MOZAK ,  Kevin B. MOORE ,  John V. LOVELACE ,  Theodore Z. SCHOENBORN ,  Bryan L. SPRY ,  Christopher E. YUNKER

IPC分类号： G11C5/14

CPC分类号： G11C11/4091 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4099

摘要： Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

公开(公告)号：US20110141827A1

公开(公告)日：2011-06-16

申请号：US12638887

申请日：2009-12-15

申请人： Christopher Mozak ,  Kevin Moore ,  John V. Lovelace ,  Zale Theodore Schoenborn ,  Bryan L. Spry ,  Chris Yunker

发明人： Christopher Mozak ,  Kevin Moore ,  John V. Lovelace ,  Zale Theodore Schoenborn ,  Bryan L. Spry ,  Chris Yunker

IPC分类号： G11C5/14

CPC分类号： G11C11/4091 ,  G11C5/147 ,  G11C11/4074 ,  G11C11/4093 ,  G11C11/4099

摘要： Described herein is an apparatus for dynamically adjusting a voltage reference level for optimizing an I/O system to achieve a certain performance metric. The apparatus comprises: a voltage reference generator to generate a voltage reference; and a dynamic voltage reference control unit, coupled with the voltage reference generator, to dynamically adjust a level of the voltage reference in response to an event. The apparatus is used to perform the method comprising: generating a voltage reference for an input/output (I/O) system; determining a worst case voltage level of the voltage reference; dynamically adjusting, via a dynamic voltage reference control unit, the voltage reference level based on determining the worst case voltage level; and computing a center of an asymmetrical eye based on the dynamically adjusted voltage reference level.

摘要翻译： 这里描述了一种用于动态调整电压参考电平以便优化I / O系统以实现某一性能度量的装置。 该装置包括：电压基准发生器，用于产生电压基准; 以及与电压参考发生器耦合的动态电压参考控制单元，以响应于事件来动态地调整电压参考电平。 该装置用于执行该方法，包括：产生用于输入/输出（I / O）系统的电压基准; 确定电压基准的最坏情况电压电平; 基于确定最坏情况电压电平，通过动态电压基准控制单元动态调整电压参考电平; 以及基于动态调整的电压参考电平计算不对称眼睛的中心。

公开(公告)号：US07590805B2

公开(公告)日：2009-09-15

申请号：US11323368

申请日：2005-12-29

申请人： Krishnakanth V. Sistla ,  Bryan L. Spry

发明人： Krishnakanth V. Sistla ,  Bryan L. Spry

IPC分类号： G06F13/00

CPC分类号： G06F12/084 ,  G06F12/0822 ,  G06F12/0831 ,  G06F2212/306

摘要： A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always able to complete a monitor transaction without requiring self snooping through the system interconnect.

摘要翻译： 当处理器采用包含共享的最后一级高速缓存时，实现监视器原语的方法和装置。 通过采用包容性最后一级缓存，处理器几乎总是能够完成监视器事务，而不需要通过系统互连自窥。

公开(公告)号：US20150095687A1

公开(公告)日：2015-04-02

申请号：US14040316

申请日：2013-09-27

申请人： BRYAN L. SPRY ,  LILY P. LOOI ,  Shaun M. CONRAD

发明人： BRYAN L. SPRY ,  LILY P. LOOI ,  Shaun M. CONRAD

IPC分类号： G06F1/32

CPC分类号： G06F1/3287 ,  G06F1/3253 ,  G06F1/3278 ,  Y02D10/151 ,  Y02D10/157 ,  Y02D10/171 ,  Y02D50/20

摘要： Improved power control techniques for integrated peripheral component interconnect express (PCIe) controllers are described. In one embodiment, for example, a processor circuit may comprise an integrated PCIe controller and logic to detect a power reduction trigger, disable the integrated PCIe controller, and remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller. Other embodiments are described and claimed.

摘要翻译： 描述了用于集成外围组件互连快速（PCIe）控制器的改进的功率控制技术。 在一个实施例中，例如，处理器电路可以包括集成PCIe控制器和用于基于集成PCIe控制器的功率消除设置来检测功率降低触发，禁用集成PCIe控制器以及从集成PCIe控制器去除功率的逻辑 。 描述和要求保护其他实施例。

公开(公告)号：US08819474B2

公开(公告)日：2014-08-26

申请号：US12417828

申请日：2009-04-03

申请人： Theodore Z. Schoenborn ,  John V. Lovelace ,  Christopher P. Mozak ,  Bryan L. Spry

发明人： Theodore Z. Schoenborn ,  John V. Lovelace ,  Christopher P. Mozak ,  Bryan L. Spry

IPC分类号： G06F1/12

CPC分类号： G06F13/4243 ,  G06F13/1689

摘要： Embodiments of the invention are generally directed to systems, methods, and apparatuses for the active training of memory command timing. In some embodiments, the CMD/CTL timing is actively trained using active feedback between memory modules and the memory controller. Other embodiments are described and claimed.

摘要翻译： 本发明的实施例一般涉及用于存储器命令定时的主动训练的系统，方法和装置。 在一些实施例中，使用存储器模块和存储器控制器之间的主动反馈主动地训练CMD / CTL定时。 描述和要求保护其他实施例。

公开(公告)号：US08331176B2

公开(公告)日：2012-12-11

申请号：US12628103

申请日：2009-11-30

申请人： Christopher P. Mozak ,  Kevin B. Moore ,  John V. Lovelace ,  Zale Theodore Schoenborn ,  Bryan L. Spry ,  Christopher E. Yunker

发明人： Christopher P. Mozak ,  Kevin B. Moore ,  John V. Lovelace ,  Zale Theodore Schoenborn ,  Bryan L. Spry ,  Christopher E. Yunker

IPC分类号： G11C29/00

CPC分类号： G11C29/02 ,  G11C29/023 ,  G11C29/028

摘要： In an embodiment, the effect of signal phase difference on a memory system is tested for various operating states. The various operating states may be represented as respective sample points on a plane defined by a range of values for a difference in signal phases and a range of values for another operating state parameter. In various embodiments, sample points for a round of crosstalk testing may include two sample points which are offset from the same reference point on the plane along different respective axes, where the axes are oblique to one another.

摘要翻译： 在一个实施例中，针对各种操作状态测试信号相位差对存储器系统的影响。 各种操作状态可以被表示为由用于信号相位差和用于另一操作状态参数的值的范围的值的范围所限定的平面上的相应采样点。 在各种实施例中，用于一轮串扰测试的采样点可以包括两个采样点，这两个采样点沿着不同相应轴的平面上的相同参考点偏移，其中轴彼此倾斜。