公开(公告)号：US20110238934A1

公开(公告)日：2011-09-29

申请号：US12748600

申请日：2010-03-29

Applicant: Kun Xu ,  David B Kramer ,  James A. Welker

Inventor： Kun Xu ,  David B Kramer ,  James A. Welker

IPC: G06F12/00

CPC classification number: G06F13/1689 ,  G06F12/0215

Abstract: A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The scheduler is operated using a clock signal with a frequency different from the frequency of the clock signal used to operate the memory controller. The clock signal used to clock the scheduler can have a lower frequency than the clock used by a memory controller. As a result, the scheduler is able to consider a greater number of pending memory access requests when selecting the next pending memory access request to be submitted to the memory for servicing and thus the resulting sequence of selected memory access requests is more likely to be optimized for memory access throughput.

Abstract translation: 数据处理系统使用调度器来调度待执行的存储器访问请求和存储器控制器来服务预定的未决存储器访问请求。 存储器访问请求相对于存储器的时钟被异步调度。 使用频率不同于用于操作存储器控制器的时钟信号的频率的时钟信号来操作调度器。 用于时钟调度器的时钟信号的频率可能低于存储器控制器使用的时钟频率。 因此，当选择要提交给存储器进行服务的下一个未决的存储器访问请求时，调度器能够考虑更多数量的待处理存储器访问请求，因此所选择的存储器访问请求的结果序列更有可能被优化 用于内存访问吞吐量。

公开(公告)号：US08572322B2

公开(公告)日：2013-10-29

申请号：US12748600

申请日：2010-03-29

Applicant: Kun Xu ,  David B Kramer ,  James A. Welker

Inventor： Kun Xu ,  David B Kramer ,  James A. Welker

IPC: G06F13/12

CPC classification number: G06F13/1689 ,  G06F12/0215

Abstract: A data processing system employs a scheduler to schedule pending memory access requests and a memory controller to service scheduled pending memory access requests. The memory access requests are asynchronously scheduled with respect to the clocking of the memory. The scheduler is operated using a clock signal with a frequency different from the frequency of the clock signal used to operate the memory controller. The clock signal used to clock the scheduler can have a lower frequency than the clock used by a memory controller. As a result, the scheduler is able to consider a greater number of pending memory access requests when selecting the next pending memory access request to be submitted to the memory for servicing and thus the resulting sequence of selected memory access requests is more likely to be optimized for memory access throughput.

Abstract translation: 数据处理系统使用调度器来调度待执行的存储器访问请求和存储器控制器来服务预定的未决存储器访问请求。 存储器访问请求相对于存储器的时钟被异步调度。 使用频率不同于用于操作存储器控制器的时钟信号的频率的时钟信号来操作调度器。 用于时钟调度器的时钟信号的频率可能低于存储器控制器使用的时钟频率。 因此，当选择要提交给存储器进行服务的下一个未决的存储器访问请求时，调度器能够考虑更多数量的待处理存储器访问请求，因此所得到的存储器访问请求的顺序更有可能被优化 用于内存访问吞吐量。

公开(公告)号：US08560796B2

公开(公告)日：2013-10-15

申请号：US12748617

申请日：2010-03-29

Applicant: Kun Xu ,  David B Kramer

Inventor： Kun Xu ,  David B Kramer

IPC: G06F13/18

CPC classification number: G06F13/1689 ,  G06F12/0215

Abstract: A data processing system employs an improved arbitration process in selecting pending memory access requests received from the one or more processor cores for servicing by the memory. The arbitration process uses memory timing and state information pertaining both to memory access requests already submitted to the memory for servicing and to the pending memory access requests which have not yet been selected for servicing by the memory. The memory timing and state information may be predicted memory timing and state information; that is, the component of the data processing system that implements the improved scheduling algorithm may not be able to determine the exact point in time at which a memory controller initiates a memory access for a corresponding memory access request and thus the component maintains information that estimates or otherwise predicts the particular state of the memory at any given time.

Abstract translation: 数据处理系统采用改进的仲裁过程来选择从一个或多个处理器核心接收到的待存储器访问请求，以便由存储器进行服务。 仲裁过程使用与已经提交到存储器进行服务的存储器访问请求有关的存储器定时和状态信息以及尚未被存储器维护的未决存储器访问请求。 存储器定时和状态信息可以是预测的存储器定时和状态信息; 也就是说，实现改进的调度算法的数据处理系统的组件可能不能够确定存储器控制器针对相应的存储器访问请求启动存储器访问的确切时间点，因此该组件保持估计的信息 或以其他方式预测在任何给定时间的存储器的特定状态。

公开(公告)号：US07116680B1

公开(公告)日：2006-10-03

申请号：US09798112

申请日：2001-03-02

Applicant: David B Kramer ,  David P Sonnier

Inventor： David B Kramer ,  David P Sonnier

IPC: H04L12/56 ,  H04J3/22

CPC classification number: H04L47/56 ,  H04L12/5601 ,  H04L47/36 ,  H04L47/50 ,  H04L49/3072 ,  H04L49/309 ,  H04L49/608 ,  H04L2012/5679 ,  H04L2012/5681

Abstract: A process and architecture to simplify the implementation of a high-speed scheduler. A traditional packet based scheduler works the length of the packet. Instead, the present invention uses a transmit queue that determines how many times a portion of a packet needs to be transmitted independent of the process to modify or transform the packet. The packet could be an ATM cell, it could be a fabric cell, or it could be a portion of a frame-based transmission of the packet. As a result, the transmit queue need only determine how many times (times to transmit (TTT)) to schedule transmission of part of the packet. The determined TTT from the transit queue takes into account the packet-based modifications that will be performed on the packet. The TTT is used to determine how many cells the packet needs to be divided into. In another illustrative embodiment, the number of cells or the TTT is determined prior to adding or removing data from the packet. In a further illustrative embodiment, the transmit queue is separate from the circuitry that modifies the packet. In other words, determining the TTT for a packet is separate from the process of modifying the packet for transmission.

Abstract translation: 一种简化高速调度器实现的过程和架构。 传统的基于分组的调度器工作包的长度。 相反，本发明使用发送队列，其确定分组的一部分需要多少次发送，独立于修改或转换分组的处理。 分组可以是ATM信元，它可以是结构小区，或者它可以是分组的基于帧的传输的一部分。 因此，发送队列只需要确定多少次（传输次数（TTT））来调度部分数据包的传输。 来自传输队列的确定的TTT考虑了将在分组上执行的基于分组的修改。 TTT用于确定数据包需要分成多少个单元。 在另一示例性实施例中，在从分组添加或移除数据之前确定小区数目或TTT。 在另一说明性实施例中，发送队列与修改分组的电路分离。 换句话说，确定分组的TTT与修改分组以进行传输的过程是分开的。