公开(公告)号：US5883417A

公开(公告)日：1999-03-16

申请号：US671362

申请日：1996-06-27

申请人： Kuo-Hao Jao ,  Yung-Shun Chen

发明人： Kuo-Hao Jao ,  Yung-Shun Chen

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/119

CPC分类号： H01L27/11 ,  H01L27/1112

摘要： The inventive SRAM cell has a poly-load resistor which comprises a thick supply voltage (Vcc) interconnect, a thick driver interconnect on a thin load resistance region which is electrically connected to both interconnects. The novel poly-load resistor overcomes the problem of lateral diffusion from the interconnect regions into the load region. The resulting SRAM cell has a low Vcc interconnect resistance.

公开(公告)号：US5885862A

公开(公告)日：1999-03-23

申请号：US81399

申请日：1998-05-19

申请人： Kuo-Hao Jao ,  Yung-Shun Chen

发明人： Kuo-Hao Jao ,  Yung-Shun Chen

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L21/70

CPC分类号： H01L27/11 ,  H01L27/1112

摘要： The inventive SRAM cell has a poly-load resistor which comprises a thick supply voltage (Vcc) interconnect, a thick driver interconnect on a thin load resistance region which is electrically connected to both interconnects. The novel poly-load resistor overcomes the problem of lateral diffusion from the interconnect regions into the load region. The resulting SRAM cell has a low Vcc interconnect resistance.

摘要翻译： 本发明的SRAM单元具有多负载电阻，其包括厚电源电压（Vcc）互连，薄电阻连接到两个互连的薄负载电阻区上的厚驱动器互连。 新型多负载电阻器克服了从互连区域向负载区域的横向扩散的问题。 所得到的SRAM单元具有低Vcc互连电阻。

公开(公告)号：US06664580B2

公开(公告)日：2003-12-16

申请号：US10267270

申请日：2002-10-09

申请人： Kuo-Hao Jao

发明人： Kuo-Hao Jao

IPC分类号： H01L27108

CPC分类号： H01L28/40 ,  H01L21/76229 ,  H01L27/0629

摘要： A new method is provided for the creation of PIP capacitors for mixed-mode processes. The process starts with the creation of Shallow Trench Isolation regions in the surface of a substrate, defining active regions and the region over which the PIP capacitor is to be created on the surface of the substrate. The PIP STI region is etched, lowering the surface of the PIP STI region. A first layer of polysilicon is selectively deposited in the opening created in the layer of STI over which the PIP is to be created, the first layer of polysilicon is polished. The wells for the isolation of the gate electrode and the PIP STI region are implanted in the surface of the substrate. A layer of insulation, serving as the layer of dielectric for the capacitor, is blanket deposited over the surface of the substrate. The deposited layer of insulation is patterned and etched, leaving the layer of insulation in place overlying the first layer of polysilicon. The mixed-mode process is then resumed with conventional processing of creation of a layer of gate oxide, the deposition and patterning of a second layer of polysilicon and the additional Back-End-Of-Line (BEOL) processing that is required to complete the mixed mode structure of a PIP capacitor and a gate electrode.

公开(公告)号：US06492224B1

公开(公告)日：2002-12-10

申请号：US09905139

申请日：2001-07-16

申请人： Kuo-Hao Jao

发明人： Kuo-Hao Jao

IPC分类号： H01L218242

CPC分类号： H01L28/40 ,  H01L21/76229 ,  H01L27/0629

摘要： A new method is provided for the creation of PIP capacitors for mixed-mode processes. The process starts with the creation of Shallow Trench Isolation regions in the surface of a substrate, defining active regions and the region over which the PIP capacitor is to be created on the surface of the substrate. The PIP STI region is etched, lowering the surface of the PIP STI region. A first layer of polysilicon is selectively deposited in the opening created in the layer of STI over which the PIP is to be created, the first layer of polysilicon is polished. The wells for the isolation of the gate electrode and the PIP STI region are implanted in the surface of the substrate. A layer of insulation, serving as the layer of dielectric for the capacitor, is blanket deposited over the surface of the substrate. The deposited layer of insulation is patterned and etched, leaving the layer of insulation in place overlying the first layer of polysilicon. The mixed-mode process is then resumed with conventional processing of creation of a layer of gate oxide, the deposition and patterning of a second layer of polysilicon and the additional Back-End-Of-Line (BEOL) processing that is required to complete the mixed mode structure of a PIP capacitor and a gate electrode.

摘要翻译： 提供了一种用于混合模式工艺创建PIP电容器的新方法。 该过程开始于在衬底的表面中形成浅沟槽隔离区域，限定有源区域和在衬底的表面上将产生PIP电容器的区域。 蚀刻PIP STI区域，降低PIP STI区域的表面。 第一层多晶硅选择性沉积在产生PIP的STI层中产生的开口中，第一层多晶硅被抛光。 用于隔离栅电极和PIP STI区的阱被注入到衬底的表面中。 用作电容器的电介质层的绝缘层被覆盖在衬底的表面上。 将沉积的绝缘层图案化和蚀刻，使绝缘层保留在第一层多晶硅上。 然后通过常规的栅极氧化层的形成，第二层多晶硅层的沉积和图案化以及额外的后端（Line-Of-Line，BEOL）处理来恢复混合模式工艺，该工艺是完成 PIP电容器和栅电极的混合模式结构。