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公开(公告)号：US07332775B2
公开(公告)日：2008-02-19
申请号：US11542864
申请日：2006-10-04
IPC分类号： H01L31/119 , H01L21/336
CPC分类号： H01L21/76897 , H01L29/665 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.
摘要翻译： 在栅电极结构的顶表面上方突出的突出间隔物在用于形成自对准接触的蚀刻工艺期间提供增强的栅电极的暴露电阻。 可以使用非晶碳牺牲层作为图案化栅极电极结构的顶层来形成突出间隔物。 电介质间隔物与栅电极结构一起形成，包括在牺牲无定形碳层的旁边。 电介质隔离层基本上延伸到无定形碳层的顶部。 然后去除无定形碳层，使得剩余的栅极结构包括具有在剩余栅极结构的顶表面上方突出的突出部分的电介质间隔物。 可以在栅极结构上形成氮化物层。 这种结构防止了在形成自对准触点时栅电极的暴露，并且一旦接触开口被填充就会短路。
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公开(公告)号：US07126198B2
公开(公告)日：2006-10-24
申请号：US10234354
申请日：2002-09-03
IPC分类号： H01L31/119 , H01L23/52 , H01L21/3205 , H01L21/44
CPC分类号： H01L21/76897 , H01L29/665 , H01L29/66545 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.
摘要翻译： 在栅电极结构的顶表面上方突出的突出间隔物在用于形成自对准接触的蚀刻工艺期间提供增强的栅电极的暴露电阻。 可以使用非晶碳牺牲层作为图案化栅极电极结构的顶层来形成突出间隔物。 电介质间隔物与栅电极结构一起形成，包括在牺牲无定形碳层的旁边。 电介质隔离层基本上延伸到无定形碳层的顶部。 然后去除无定形碳层，使得剩余的栅极结构包括具有在剩余栅极结构的顶表面上方突出的突出部分的电介质间隔物。 可以在栅极结构上形成氮化物层。 这种结构防止了在形成自对准触点时栅电极的暴露，并且一旦接触开口被填充就会短路。
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公开(公告)号：US07261745B2
公开(公告)日：2007-08-28
申请号：US10675572
申请日：2003-09-30
CPC分类号： H01J37/32935 , H01L21/31138 , H01L21/32139 , H01L21/67069 , H01L21/67253 , Y10T29/41
摘要： A process and apparatus for controlling an etchant gas concentration in an etch chamber. The etchant gas concentration and an inert gas concentration are determined and the latter concentration is used to normalize the etchant gas concentration. The normalized value is compared with a predetermined reference value and the flow of etchant gas into the chamber is controlled in response thereto.
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公开(公告)号：US07632690B2
公开(公告)日：2009-12-15
申请号：US11827807
申请日：2007-07-13
IPC分类号： H01L21/00
CPC分类号： H01J37/32935 , H01L21/31138 , H01L21/32139 , H01L21/67069 , H01L21/67253 , Y10T29/41
摘要： A process and apparatus for controlling an etchant gas concentration in an etch chamber. The etchant gas concentration and an inert gas concentration are determined and the latter concentration is used to normalize the etchant gas concentration. The normalized value is compared with a predetermined reference value and the flow of etchant gas into the chamber is controlled in response thereto.
摘要翻译： 用于控制蚀刻室中的蚀刻剂气体浓度的方法和装置。 确定蚀刻剂气体浓度和惰性气体浓度，并将后一浓度用于归一化蚀刻剂气体浓度。 将归一化值与预定的参考值进行比较，并且响应于此而控制蚀刻剂进入腔室的流动。
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公开(公告)号：US6110395A
公开(公告)日：2000-08-29
申请号：US918852
申请日：1997-08-26
CPC分类号： H01J37/32522 , H01J37/32623 , H01J37/3266 , H05H1/46
摘要： The present invention relates to a method and structure for controlling plasma uniformity in plasma processing applications. Electron thermal conductivity parallel and perpendicular to magnetic field lines differs by orders of magnitude for low magnetic fields (on the order of 10 gauss). This property allows the directing of heat flux by controlling the magnetic field configuration independent of ions since the effect of modest magnetic fields upon the transport of ions themselves is minimal. Heat is preferentially conducted along magnetic field lines with electron temperatures on the order of 0.1 to 1 eV/cm being sufficient to drive kilowatt-level heat fluxes across areas typical of plasma processing source dimensions.
摘要翻译： 本发明涉及一种用于控制等离子体处理应用中的等离子体均匀性的方法和结构。 与磁场线平行且垂直的电子热导率对于低磁场（大约10高斯）的数量级不同。 该性质允许通过独立于离子控制磁场构造来引导热通量，因为适度的磁场对离子本身的输送的影响是最小的。 热量优先沿着磁场线传导，电子温度为0.1至1eV / cm左右，足以在等离子体处理源尺寸典型的区域上驱动千瓦级热通量。
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公开(公告)号：US06362094B1
公开(公告)日：2002-03-26
申请号：US09640329
申请日：2000-08-16
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76832 , H01L21/76834 , H01L21/76837
摘要： The present invention provides a method of fabricating a self-aligning contact opening comprising: (a) forming a dielectric layer over a semiconductor substrate and gate electrodes located on the semiconductor substrate, (b) forming a carbide liner over the dielectric layer, and (c) etching at least a portion the carbide liner to form a self-aligning contact opening between the gate electrodes.
摘要翻译： 本发明提供一种制造自对准接触开口的方法，包括：（a）在半导体衬底上形成电介质层和位于半导体衬底上的栅电极，（b）在电介质层上形成碳化物衬垫，以及（ c）蚀刻碳化物衬垫的至少一部分以在栅电极之间形成自对准接触开口。
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7.发明授权High-density field emission elements and a method for forming said emission elements 有权高密度场发射元件和形成所述发射元件的方法公开(公告)号：US07981305B2
公开(公告)日：2011-07-19
申请号：US12506090
申请日：2009-07-20
IPC分类号： B44C1/22 , G01L21/30 , H01L21/302
CPC分类号： H01J9/025 , H01J1/3044
摘要： A method for forming high density emission elements and field emission displays formed according to the method. Oxygen and a silicon etchant are introduced into a plasma etching chamber containing a silicon substrate. The oxygen reacts with the silicon surface to form regions of silicon dioxide, while the silicon etchant etches the silicon to form the emission elements. The silicon dioxide regions mask the underlying silicon during the silicon etch process. High density and high aspect ratio emission elements are formed without using photolithographic processes. The emission elements formed according to the present invention provide a more uniform emission of electrons. Further, a display incorporating emission elements formed according to the present invention provides increased brightness. The reliability of the display is increased due to the use of a plurality of emission elements to supply electrons for stimulating the phosphor substrate material to produce the image.
摘要翻译： 根据该方法形成高密度发射元件和场致发射显示器的方法。 将氧和硅蚀刻剂引入含有硅衬底的等离子体蚀刻室中。 氧与硅表面反应形成二氧化硅区，而硅蚀刻剂蚀刻硅以形成发射元件。 在硅蚀刻工艺期间，二氧化硅区域掩盖下面的硅。 在不使用光刻工艺的情况下形成高密度和高纵横比的发光元件。 根据本发明形成的发射元件提供更均匀的电子发射。 此外，包含根据本发明形成的发射元件的显示器提供增加的亮度。 由于使用多个发射元件来供应电子以刺激磷光体基底材料以产生图像，显示器的可靠性增加。
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8.发明授权High-density field emission elements and a method for forming said emission elements 失效高密度场发射元件和形成所述发射元件的方法公开(公告)号：US07564178B2
公开(公告)日：2009-07-21
申请号：US11057690
申请日：2005-02-14
CPC分类号： H01J9/025 , H01J1/3044
摘要： A method for forming high density emission elements for a field emission display and field emission elements and field emission displays formed according to the method. Oxygen and a silicon etchant are introduced into a plasma etching chamber containing a silicon substrate. The oxygen reacts with the silicon surface to form regions of silicon dioxide, while the silicon etchant etches the silicon to form the emission elements. The silicon dioxide regions mask the underlying silicon during the silicon etch process. High density and high aspect ratio emission elements are formed without using photolithographic processes as practiced in the prior art. The emission elements formed according to the present invention provide a more uniform emission of electrons than the prior art techniques. Further, a display incorporating emission elements formed according to the present invention provides increased brightness. Further, the reliability of the display is increased due to the use of a plurality of emission elements to supply electrons for stimulating the phosphor substrate material to produce the image.
摘要翻译： 一种用于形成用于场发射显示的高密度发射元件和根据该方法形成的场发射元件和场发射显示器的方法。 将氧和硅蚀刻剂引入含有硅衬底的等离子体蚀刻室中。 氧与硅表面反应形成二氧化硅区，而硅蚀刻剂蚀刻硅以形成发射元件。 在硅蚀刻工艺期间，二氧化硅区域掩盖下面的硅。 在不使用现有技术中实施的光刻工艺的情况下，形成高密度和高纵横比的发光元件。 根据本发明形成的发射元件提供比现有技术更均匀的电子发射。 此外，包含根据本发明形成的发射元件的显示器提供增加的亮度。 此外，由于使用多个发射元件来提供显示器的可靠性，以提供用于刺激荧光体基底材料以产生图像的电子。
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9.发明授权公开(公告)号：US07087498B2
公开(公告)日：2006-08-08
申请号：US10675259
申请日：2003-09-30
申请人： Mario Pita , Milton Beachy , Gerald W. Gibson, Jr.
发明人： Mario Pita , Milton Beachy , Gerald W. Gibson, Jr.
IPC分类号： H01L21/302
CPC分类号： H01L21/3081 , H01L21/3065 , H01L21/3085
摘要： A method for forming a trench in a semiconductor silicon substrate. An anti-reflective coating layer and a photoresist layer are formed over the substrate and patterned in accordance with a location for the trench. During the trench etch into the silicon substrate, the etch environment is monitored to detect the material of the anti-reflective coating layer. The etch process is controlled in response to detecting the removal of this material and the known etch rate differential between the anti-reflective coating material layer and the silicon substrate.
摘要翻译： 一种在半导体硅衬底中形成沟槽的方法。 在衬底上形成抗反射涂层和光致抗蚀剂层，并根据沟槽的位置进行图案化。 在沟槽蚀刻进入硅衬底期间，监测蚀刻环境以检测抗反射涂层的材料。 响应于检测到该材料的去除以及抗反射涂层材料层和硅衬底之间的已知蚀刻速率差异来控制蚀刻工艺。
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