公开(公告)号：US08431462B2

公开(公告)日：2013-04-30

申请号：US13183630

申请日：2011-07-15

申请人： Kwan-Heum Lee ,  Soon-Wook Jung ,  Jung-Hyun Park ,  Wook-Je Kim ,  Jong-Sang Ban

发明人： Kwan-Heum Lee ,  Soon-Wook Jung ,  Jung-Hyun Park ,  Wook-Je Kim ,  Jong-Sang Ban

IPC分类号： H01L21/337 ,  H01L21/8238 ,  H01L21/336 ,  H01L27/12

CPC分类号： H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

摘要： A method of manufacturing a semiconductor device includes forming a gate structure on a substrate; forming a sacrificial spacer may be formed on a sidewall of the gate substrate; implanting first impurities into portions of the substrate by a first ion implantation process using the gate structure and the sacrificial spacer as ion implantation masks to form source and drain regions; removing the sacrificial spacer; and implanting second impurities and carbon atoms into portions of the substrate by a second ion implantation process using the gate structure as an ion implantation mask to form source and drain extension regions and carbon doping regions, respectively.

摘要翻译： 一种制造半导体器件的方法包括在衬底上形成栅极结构; 形成牺牲隔离物可以形成在栅极衬底的侧壁上; 通过使用栅极结构和牺牲隔离物作为离子注入掩模的第一离子注入工艺将第一杂质注入到衬底的部分中以形成源区和漏区; 去除牺牲隔离物; 以及通过使用所述栅极结构作为离子注入掩模的第二离子注入工艺将第二杂质和碳原子注入到所述衬底的部分中，以分别形成源极和漏极延伸区域和碳掺杂区域。

公开(公告)号：US09112054B2

公开(公告)日：2015-08-18

申请号：US13181907

申请日：2011-07-13

申请人： Kwan-Heum Lee ,  Wook-Je Kim ,  Soon-Wook Jung ,  Sang-Bom Kang ,  Ki-Hong Kim

发明人： Kwan-Heum Lee ,  Wook-Je Kim ,  Soon-Wook Jung ,  Sang-Bom Kang ,  Ki-Hong Kim

IPC分类号： H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L29/7848

摘要： A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.

摘要翻译： 提供半导体器件和制造半导体器件的方法。 在制造半导体器件的方法中，在衬底上形成栅极结构。 在与栅极结构相邻的衬底的顶表面上形成外延层。 通过使用栅极结构作为离子注入掩模，将外延层中的杂质和碳注入到衬底的上部，形成升高的源极/漏极（ESD）层和杂质区。 在ESD层上形成金属硅化物层。

公开(公告)号：US08300445B2

公开(公告)日：2012-10-30

申请号：US12746473

申请日：2008-12-04

申请人： Kyung-Jin Lee ,  Hyun-Woo Lee ,  Soon-Wook Jung

发明人： Kyung-Jin Lee ,  Hyun-Woo Lee ,  Soon-Wook Jung

IPC分类号： G11C19/00

CPC分类号： G11C11/14 ,  B82Y10/00 ,  G11C11/5607 ,  G11C19/0808

摘要： Disclosed herein are a nanowire and a current-induced domain wall displacement-type memory device using the same. The nanowire has perpendicular magnetic anisotropy and is configured in a manner that when a parameter Q, calculated by a saturation magnetization per unit area, a domain wall thickness and a spin polarizability of a ferromagnet that is a constituent material of the nanowire, has a value of (formula 1 should be inserted here) a domain wall thickness, a width “*′” and a thickness −* of the nanowire satisfy the relationship of (formula 2 should be inserted here) The present invention can be designed such that a current density capable of driving a memory device utilizing the current-driven domain wall displacement has a value of less than (formula 3 should be inserted here), through the determination of the optimal nanowire width and thickness satisfying a value of a critical current density, Jc for the domain wall displacement below a certain value required for commercialization, for a given material in the nanowire with perpendicular anisotropy. According to such a configuration of the present invention, the current density required for the domain wall displacement can be at least 10 times or further lowered than the current density in currently available nano wires. Therefore, the present invention is capable of solving the problems associated with high power consumption and malfunction of the device due to generation of Joule heat and is also capable of achieving low-cost production of memory devices. 3 × 10 8 ⁢ ⁢ A ⁢ / ⁢ cm 2 ≤ Q ≤ 10 9 ⁢ ⁢ A ⁢ / ⁢ cm 2 , ( 1 ) 1.39 T / λ + 4.51 ≤ W λ ≤ 1.53 T / λ + 4.44 ( 2 ) 10 7 ⁢ ⁢ A ⁢ / ⁢ cm 2 , ( 3 )

摘要翻译： 本文公开了使用其的纳米线和电流诱导畴壁位移型存储器件。 纳米线具有垂直磁各向异性，并且以如下方式配置：当由单位面积的饱和磁化强度计算的参数Q为作为纳米线的构成材料的铁磁体的畴壁厚度和自旋极化率时，具有值 （式1中应插入）畴壁厚度，纳米线的宽度*'和厚度 - *满足（式2应插入）的关系本发明可以设计成使得电流密度能够 通过确定满足临界电流密度值的最佳纳米线宽度和厚度，使用电流驱动畴壁位移来驱动存储器件的值小于（这里应插入公式3），对于 对于具有垂直各向异性的纳米线中的给定材料，畴壁位移低于商业化所需的一定值。 根据本发明的这种结构，畴壁位移所需的电流密度可以是目前可用的纳米线中的电流密度的10倍以上。 因此，本发明能够解决由于焦耳热的产生而导致的高功耗和故障的问题，并且也能够实现低成本地生产存储器件。 3×10 8突发A / cm 2≤Q≤109令A / cm 2，（1）1.39 T /λ+4.51≤Wλ≤1.53T/λ+ 4.44（2）10 7 唔A / cm 2，（3）

公开(公告)号：US20080029892A1

公开(公告)日：2008-02-07

申请号：US11832310

申请日：2007-08-01

申请人： Soon-Wook Jung

发明人： Soon-Wook Jung

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/28556 ,  H01L21/02063 ,  H01L21/76802 ,  H01L21/76814 ,  H01L21/7685

摘要： A method of fabricating a semiconductor device including at least one of the following steps: Forming a metal layer on and/over a semiconductor substrate. Forming a diffusion barrier film on and/over the metal layer. Forming a metal layer pattern and an diffusion barrier film pattern by etching the metal layer and the diffusion barrier film. Forming an insulating film covering the metal layer pattern and the diffusion barrier film pattern. Forming a via hole using a photoresist pattern on and/or over the insulating film. Forming a contact by filling the via hole with an electrically conductive material.

摘要翻译： 一种制造半导体器件的方法，包括以下步骤中的至少一个：在半导体衬底上和/之上形成金属层。 在金属层上和/之上形成扩散阻挡膜。 通过蚀刻金属层和扩散阻挡膜来形成金属层图案和扩散阻挡膜图案。 形成覆盖金属层图案和扩散阻挡膜图案的绝缘膜。 在绝缘膜上和/或上方形成使用光致抗蚀剂图案的通孔。 通过用导电材料填充通孔形成接触。

公开(公告)号：US20110007559A1

公开(公告)日：2011-01-13

申请号：US12746473

申请日：2008-12-04

申请人： Kyung-Jin Lee ,  Hyun-Woo Lee ,  Soon-Wook Jung

发明人： Kyung-Jin Lee ,  Hyun-Woo Lee ,  Soon-Wook Jung

IPC分类号： G11C11/14 ,  H01B5/02

CPC分类号： G11C11/14 ,  B82Y10/00 ,  G11C11/5607 ,  G11C19/0808

摘要： Disclosed herein are a nanowire and a current-induced domain wall displacement-type memory device using the same. The nanowire has perpendicular magnetic anisotropy and is configured in a manner that when a parameter Q, calculated by a saturation magnetization per unit area, a domain wall thickness and a spin polarizability of a ferromagnet that is a constituent material of the nanowire, has a value of (formula 1 should be inserted here) a domain wall thickness, a width “*′” and a thickness −* of the nanowire satisfy the relationship of (formula 2 should be inserted here) The present invention can be designed such that a current density capable of driving a memory device utilizing the current-driven domain wall displacement has a value of less than (formula 3 should be inserted here), through the determination of the optimal nanowire width and thickness satisfying a value of a critical current density, Jc for the domain wall displacement below a certain value required for commercialization, for a given material in the nanowire with perpendicular anisotropy. According to such a configuration of the present invention, the current density required for the domain wall displacement can be at least 10 times or further lowered than the current density in currently available nano wires. Therefore, the present invention is capable of solving the problems associated with high power consumption and malfunction of the device due to generation of Joule heat and is also capable of achieving low-cost production of memory devices. 3 × 10 8  A  /  cm 2 ≤ Q ≤ 10 9  A  /  cm 2 , ( 1 ) 1.39 T / λ + 4.51 ≤ W λ ≤ 1.53 T / λ + 4.44 ( 2 ) 10 7  A  /  cm 2 , ( 3 )

摘要翻译： 本文公开了使用其的纳米线和电流诱导畴壁位移型存储器件。 纳米线具有垂直磁各向异性，并且以如下方式配置：当由单位面积的饱和磁化强度计算的参数Q为作为纳米线的构成材料的铁磁体的畴壁厚度和自旋极化率时，具有值 （式1应该插入）畴壁厚度，宽度“*”“和纳米线的厚度 - *满足关系（式2应该插在这里）本发明可以被设计成使得电流 通过确定满足临界电流密度值的最佳纳米线宽度和厚度，能够利用电流驱动畴壁位移驱动存储器件的密度具有小于（在此应插入公式3）的值Jc 对于具有垂直各向异性的纳米线中的给定材料，域壁位移低于商业化所需的一定值。 根据本发明的这种结构，畴壁位移所需的电流密度可以是目前可用的纳米线中的电流密度的10倍以上。 因此，本发明能够解决由于焦耳热的产生而导致的高功耗和故障的问题，并且也能够实现低成本地生产存储器件。 3×10 8 A / cm 2≤Q≤109 A / cm 2，（1）1.39 T /λ+4.51≤Wλ≤1.53T /λ+ 4.44（2）10 7 / cm 2，（3）