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    Method of etching polysilicon layer
    1.
    发明授权
    Method of etching polysilicon layer 失效
    蚀刻多晶硅层的方法

    公开(公告)号：US5951879A

    公开(公告)日：1999-09-14

    申请号：US631003

    申请日：1996-04-12

    申请人： Kyoko Miyamoto ,  Satoshi Nakagawa

    发明人： Kyoko Miyamoto ,  Satoshi Nakagawa

    IPC分类号： H05H1/46 ,  C23F4/00 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3213 ,  H01L29/78 ,  H01L2/302

    CPC分类号： H01L21/32137

    摘要： A highly reliable semiconductor IC circuit can be produced by this etching method: A resist layer is formed on a polysilicon layer which is formed on a silicon dioxide layer on a silicon substrate. The resist layer is used as a mask, and silicon oxide layer deposits thereon while polysilicon layer is being etched. Carbon emission out of the resist layer is thus restrained, and thereby a selectivity, an etching speed ratio of polysilicon layer vs. silicon dioxide layer, is substantially raised.

    摘要翻译： 可以通过该蚀刻方法制造高可靠性的半导体IC电路：在形成于硅衬底上的二氧化硅层上的多晶硅层上形成抗蚀剂层。 抗蚀剂层用作掩模，并且氧化硅层沉积在其上，同时蚀刻多晶硅层。 因此抑制了抗蚀剂层中的碳发射，从而大大提高了多晶硅层与二氧化硅层的选择性，蚀刻速度比。

    Manufacturing method of non-volatile semiconductor memory devices
    3.
    发明授权
    Manufacturing method of non-volatile semiconductor memory devices 失效
    非易失性半导体存储器件的制造方法

    公开(公告)号：US5491101A

    公开(公告)日：1996-02-13

    申请号：US348100

    申请日：1994-11-25

    申请人： Kyoko Miyamoto ,  Fumihiko Noro

    发明人： Kyoko Miyamoto ,  Fumihiko Noro

    IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/8247

    CPC分类号： H01L29/66825 ,  H01L27/115

    摘要： The invention provides a process to form on a certain conductive type semiconductor substrate 1 insulation layer 9 having openings 11, which regions will become source and drain; a process to form diffusion layer 8 of the same conductive type as semiconductor substrate 1 in to-be-drain space, with insulation layer 9 and photoresist 10 as masks; a process to form side wall layer 13 alongside openings of insulation layer 9; a process to form diffusion layers 4 and 5, conductive type of which layers is opposite to that of semiconductor substrate 1, in to-be-source and to-be-drain regions, with insulation layer 9 and side wall layer 13 as masks; a process to remove insulation layer 9 and side wall layer 13; and a process to form insulation layer 2 on semiconductor substrate in channel region distinguished by, and including part of, diffusion layers 4 and 5, and to form floating-gate electrode 3 on insulation layer 2, and control-gate electrode 7 with insulation layer 6 in between. The manufacturing method according to this invention forms drain and high density P-type diffusion layer by making use of side wall layer. Therefore, this makes it possible to shape DSA structure controlling the distance from drain to high density P-type diffusion layer with high accuracy, without using high temperature diffusion process. This means that this invention offers an easy way to make DSA structure with finer design rules.

    摘要翻译： 本发明提供一种在具有开口11的某种导电型半导体衬底1绝缘层9上形成的工艺，该区域将成为源极和漏极; 形成与待漏极空间中的半导体衬底1相同的导电类型的扩散层8的工艺，绝缘层9和光致抗蚀剂10作为掩模; 沿着绝缘层9的开口形成侧壁层13的工艺; 形成扩散层4和5的工艺，其导电类型的层与半导体衬底1的导电类型在源极和漏极区域中，绝缘层9和侧壁层13作为掩模; 去除绝缘层9和侧壁层13的工艺; 以及在由扩散层4和5区分并包括部分扩散层4和5的沟道区域中的半导体衬底上形成绝缘层2并在绝缘层2上形成浮栅电极3的绝缘层2和具有绝缘层的控制栅电极7的工艺 6之间。 根据本发明的制造方法通过利用侧壁层形成漏极和高密度P型扩散层。 因此，能够在不使用高温扩散处理的情况下，高精度地形成控制从漏极到高密度P型扩散层的距离的DSA结构。 这意味着本发明提供了使DSA结构具有更精细的设计规则的简单方法。