公开(公告)号：US5491101A

公开(公告)日：1996-02-13

申请号：US348100

申请日：1994-11-25

申请人： Kyoko Miyamoto ,  Fumihiko Noro

发明人： Kyoko Miyamoto ,  Fumihiko Noro

IPC分类号： H01L21/336 ,  H01L27/115 ,  H01L21/8247

CPC分类号： H01L29/66825 ,  H01L27/115

摘要： The invention provides a process to form on a certain conductive type semiconductor substrate 1 insulation layer 9 having openings 11, which regions will become source and drain; a process to form diffusion layer 8 of the same conductive type as semiconductor substrate 1 in to-be-drain space, with insulation layer 9 and photoresist 10 as masks; a process to form side wall layer 13 alongside openings of insulation layer 9; a process to form diffusion layers 4 and 5, conductive type of which layers is opposite to that of semiconductor substrate 1, in to-be-source and to-be-drain regions, with insulation layer 9 and side wall layer 13 as masks; a process to remove insulation layer 9 and side wall layer 13; and a process to form insulation layer 2 on semiconductor substrate in channel region distinguished by, and including part of, diffusion layers 4 and 5, and to form floating-gate electrode 3 on insulation layer 2, and control-gate electrode 7 with insulation layer 6 in between. The manufacturing method according to this invention forms drain and high density P-type diffusion layer by making use of side wall layer. Therefore, this makes it possible to shape DSA structure controlling the distance from drain to high density P-type diffusion layer with high accuracy, without using high temperature diffusion process. This means that this invention offers an easy way to make DSA structure with finer design rules.

摘要翻译： 本发明提供一种在具有开口11的某种导电型半导体衬底1绝缘层9上形成的工艺，该区域将成为源极和漏极; 形成与待漏极空间中的半导体衬底1相同的导电类型的扩散层8的工艺，绝缘层9和光致抗蚀剂10作为掩模; 沿着绝缘层9的开口形成侧壁层13的工艺; 形成扩散层4和5的工艺，其导电类型的层与半导体衬底1的导电类型在源极和漏极区域中，绝缘层9和侧壁层13作为掩模; 去除绝缘层9和侧壁层13的工艺; 以及在由扩散层4和5区分并包括部分扩散层4和5的沟道区域中的半导体衬底上形成绝缘层2并在绝缘层2上形成浮栅电极3的绝缘层2和具有绝缘层的控制栅电极7的工艺 6之间。 根据本发明的制造方法通过利用侧壁层形成漏极和高密度P型扩散层。 因此，能够在不使用高温扩散处理的情况下，高精度地形成控制从漏极到高密度P型扩散层的距离的DSA结构。 这意味着本发明提供了使DSA结构具有更精细的设计规则的简单方法。

公开(公告)号：US6143609A

公开(公告)日：2000-11-07

申请号：US824476

申请日：1996-12-02

申请人： Kazuo Sato ,  Kenji Ueda ,  Michio Morita ,  Fumihiko Noro ,  Kyoko Miyamoto ,  Hideaki Onishi ,  Kazuo Umeda ,  Kazuya Kubo

发明人： Kazuo Sato ,  Kenji Ueda ,  Michio Morita ,  Fumihiko Noro ,  Kyoko Miyamoto ,  Hideaki Onishi ,  Kazuo Umeda ,  Kazuya Kubo

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： A floating gate type semiconductor memory and method of manufacture are described including an erasing gate electrode in which a tunneling region can be formed easily and high reliability can be kept. An active region isolated by element isolation insulating films is formed on a semiconductor substrate. A gate insulating film and a floating gate electrode are sequentially formed on the active region. A control gate electrode is formed above the floating gate electrode with a silicon oxide film disposed therebetween. A tunneling insulating film is formed only on the side wall of the floating gate electrode. Then, an erasing gate electrode is formed so as to cover the tunneling insulating film.

摘要翻译： 描述了浮栅型半导体存储器及其制造方法，其特征在于包括能够容易地形成隧道区域的擦除栅极电极，并且可以保持高的可靠性。 在半导体衬底上形成由元件隔离绝缘膜隔离的有源区。 在有源区上依次形成栅极绝缘膜和浮栅电极。 在浮置栅电极的上方形成有控制栅电极，其间配置有氧化硅膜。 隧道绝缘膜只形成在浮栅电极的侧壁上。 然后，形成擦除栅电极以覆盖隧道绝缘膜。

公开(公告)号：US5838039A

公开(公告)日：1998-11-17

申请号：US677651

申请日：1996-07-08

申请人： Kazuo Sato ,  Kenji Ueda ,  Michio Morita ,  Fumihiko Noro ,  Kyoko Miyamoto ,  Hideaki Onishi ,  Kazuo Umeda ,  Kazuya Kubo

发明人： Kazuo Sato ,  Kenji Ueda ,  Michio Morita ,  Fumihiko Noro ,  Kyoko Miyamoto ,  Hideaki Onishi ,  Kazuo Umeda ,  Kazuya Kubo

IPC分类号： H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883

摘要： A floating gate type semiconductor memory and method of manufacture are described including an erasing gate electrode in which a tunneling region can be formed easily and high reliability can be kept. An active region isolated by element isolation insulating films is formed on a semiconductor substrate. A gate insulating film and a floating gate electrode are sequentially formed on the active region. A control gate electrode is formed above the floating gate electrode with a silicon oxide film disposed therebetween. A tunneling insulating firm is formed only on the side wall of the floating gate electrode. Then, an erasing gate electrode is formed so as to cover the tunneling insulating film.

摘要翻译： 描述了浮栅型半导体存储器及其制造方法，其特征在于包括能够容易地形成隧道区域的擦除栅极电极，并且可以保持高的可靠性。 在半导体衬底上形成由元件隔离绝缘膜隔离的有源区。 在有源区上依次形成栅极绝缘膜和浮栅电极。 在浮置栅电极的上方形成有控制栅电极，其间配置有氧化硅膜。 仅在浮栅电极的侧壁上形成隧道绝缘固体。 然后，形成擦除栅电极以覆盖隧道绝缘膜。

公开(公告)号：US20080048247A1

公开(公告)日：2008-02-28

申请号：US11806887

申请日：2007-06-05

申请人： Koji Yoshida ,  Masataka Kusumi ,  Hiroaki Kuriyama ,  Fumihiko Noro ,  Nobuyoshi Takahashi

发明人： Koji Yoshida ,  Masataka Kusumi ,  Hiroaki Kuriyama ,  Fumihiko Noro ,  Nobuyoshi Takahashi

IPC分类号： H01L29/792 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L29/792 ,  H01L21/0217 ,  H01L21/02211 ,  H01L21/02222 ,  H01L21/02271 ,  H01L21/02337 ,  H01L21/28282 ,  H01L21/3125 ,  H01L21/3185 ,  H01L21/76834 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/4234 ,  H01L29/511 ,  H01L29/7923

摘要： A semiconductor device includes: source/drain regions formed in a semiconductor substrate; a trapping film for storing information by accumulating charges, the trapping film being formed in a region on the semiconductor substrate which includes a region on a channel region between the source/drain regions; and gate electrodes formed on the trapping film. A silicon nitride film containing carbon is formed by low pressure CVD using an organic material so as to cover the gate electrodes and a part of the trapping film which is located between adjacent gate electrodes.

摘要翻译： 半导体器件包括：形成在半导体衬底中的源/漏区; 用于通过累积电荷来存储信息的捕集膜，所述捕获膜形成在所述半导体衬底上的包括所述源极/漏极区之间的沟道区域上的区域的区域中; 以及形成在捕获膜上的栅电极。 通过使用有机材料的低压CVD形成含有碳的氮化硅膜，以覆盖位于相邻栅电极之间的栅电极和捕获膜的一部分。

公开(公告)号：US06867118B2

公开(公告)日：2005-03-15

申请号：US10447220

申请日：2003-05-29

申请人： Fumihiko Noro

发明人： Fumihiko Noro

IPC分类号： H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/11573

摘要： A semiconductor substrate has a memory region and a logic region isolated by an isolation insulating film. Plural memory transistors are provided in the form of a matrix in the memory region, and a logic transistor is provided in the logic region. Gate electrodes of memory transistors arranged along the word line direction out of the plural memory transistors are formed as a common gate electrode extending along the word line direction, and impurity diffusion layers working as source/drain regions of memory transistors arranged along the bit line direction are formed as a common impurity diffusion layer extending along the bit line direction. An inter-gate insulating film having its top face at a lower level than the gate electrodes is formed on the semiconductor substrate between the gate electrodes of the plural memory transistors. A sidewall insulating film is formed on the side face of a gate electrode of the logic transistor. A silicide layer is formed on the gate electrodes of the memory transistors, the gate electrode of the logic transistor and portions of the top faces, exposed from the sidewall insulating film, of impurity diffusion layers working as source/drain regions of the logic transistor.

摘要翻译： 半导体衬底具有通过隔离绝缘膜隔离的存储区域和逻辑区域。 多个存储晶体管以存储区域中的矩阵的形式提供，并且逻辑晶体管被提供在逻辑区域中。 形成沿多个存储晶体管的字线方向配置的存储晶体管的栅电极作为沿着字线方向延伸的公共栅电极，并且沿着位线方向配置的存储晶体管的源/漏区起作用的杂质扩散层 形成为沿着位线方向延伸的公共杂质扩散层。 在多个存储晶体管的栅电极之间的半导体衬底上形成具有其栅极电位较低的顶面的栅极间绝缘膜。 在逻辑晶体管的栅电极的侧面上形成侧壁绝缘膜。 在存储晶体管的栅电极，逻辑晶体管的栅电极和从侧壁绝缘膜露出的顶面的部分，形成作为逻辑晶体管的源极/漏极区的杂质扩散层的硅化物层。

公开(公告)号：US06545312B2

公开(公告)日：2003-04-08

申请号：US09897417

申请日：2001-07-03

申请人： Masataka Kusumi ,  Fumihiko Noro ,  Hiromasa Fujimoto ,  Akihiro Kamada ,  Shinji Odanaka ,  Seiki Ogura

发明人： Masataka Kusumi ,  Fumihiko Noro ,  Hiromasa Fujimoto ,  Akihiro Kamada ,  Shinji Odanaka ,  Seiki Ogura

IPC分类号： H01L29788

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/42324 ,  H01L29/7885

摘要： A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.

公开(公告)号：US20090104765A1

公开(公告)日：2009-04-23

申请号：US12337023

申请日：2008-12-17

申请人： Nobuyoshi TAKAHASHI ,  Fumihiko Noro ,  Kenji Sato

发明人： Nobuyoshi TAKAHASHI ,  Fumihiko Noro ,  Kenji Sato

IPC分类号： H01L21/768

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.

摘要翻译： 半导体器件包括：半导体区域; 多个位线扩散层，其形成在所述半导体区域的上部，并且各自沿行方向延伸; 形成在位线扩散层上的多个位线绝缘膜; 形成在所述半导体区域上的各个相邻位线扩散层之间的多个栅极绝缘膜; 以及多个字线，各自在列方向上形成在半导体区域上，并且与字线绝缘膜和栅极绝缘膜交叉。 存储单元形成在栅极绝缘膜和字线的交点处。 包括与位线扩散层电连接的连接部分的多个连接扩散层形成在半导体区域的上部，并且连接部分的上表面的电平低于连接扩散部的上表面的高度 半导体区域中的层。

公开(公告)号：US07476943B2

公开(公告)日：2009-01-13

申请号：US11405451

申请日：2006-04-18

申请人： Nobuyoshi Takahashi ,  Fumihiko Noro ,  Kenji Sato

发明人： Nobuyoshi Takahashi ,  Fumihiko Noro ,  Kenji Sato

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A semiconductor device includes: a semiconductor region; a plurality of bit line diffusion layers formed in an upper portion of the semiconductor region and each extending in a row direction; a plurality of bit line insulating films formed on the bit line diffusion layers; a plurality of gate insulting films formed between the respective adjacent bit line diffusion layers on the semiconductor region; and a plurality of word lines each formed on the semiconductor region in a column direction and each intersecting with the bit line insulating films and the gate insulating films. Memory cells are formed at intersections of the gate insulating films and the word lines. A plurality of connection diffusion layers including connection parts electrically connected to the bit line diffusion layers are formed in the upper portion of the semiconductor region, and a level of upper faces of the connection parts is lower than a level of upper faces of the connection diffusion layers in the semiconductor region.

摘要翻译： 半导体器件包括：半导体区域; 多个位线扩散层，其形成在所述半导体区域的上部，并且各自沿行方向延伸; 形成在位线扩散层上的多个位线绝缘膜; 形成在所述半导体区域上的各个相邻位线扩散层之间的多个栅极绝缘膜; 以及多个字线，各自在列方向上形成在半导体区域上，并且与字线绝缘膜和栅极绝缘膜交叉。 存储单元形成在栅极绝缘膜和字线的交点处。 包括与位线扩散层电连接的连接部分的多个连接扩散层形成在半导体区域的上部，并且连接部分的上表面的电平低于连接扩散部的上表面的高度 半导体区域中的层。

公开(公告)号：US20060086971A1

公开(公告)日：2006-04-27

申请号：US11152114

申请日：2005-06-15

申请人： Nobuyoshi Takahashi ,  Satoshi Iwamoto ,  Fumihiko Noro ,  Masatoshi Arai

发明人： Nobuyoshi Takahashi ,  Satoshi Iwamoto ,  Fumihiko Noro ,  Masatoshi Arai

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11568 ,  H01L21/823878 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11573 ,  H01L29/792 ,  Y10S438/954

摘要： A semiconductor device includes a memory section formed at a semiconductor substrate and including a first transistor having an ONO film that can store charges between the semiconductor substrate and a memory electrode and a first STI region for isolating the first transistor, and a CMOS section formed at the semiconductor substrate and including a second transistor having a CMOS electrode and a gate dielectric and a second STI region for isolating the second transistor. The height of the top surface of the first STI region is set equal to or smaller than the height of the top surface of the second STI region.

摘要翻译： 一种半导体器件包括形成在半导体衬底上的存储器部分，并且包括具有可存储半导体衬底和存储电极之间的电荷的ONO膜的第一晶体管和用于隔离第一晶体管的第一STI区域和形成在 半导体衬底并且包括具有CMOS电极和栅极电介质的第二晶体管和用于隔离第二晶体管的第二STI区域。 第一STI区域的顶表面的高度被设定为等于或小于第二STI区域的顶表面的高度。

公开(公告)号：US06872624B2

公开(公告)日：2005-03-29

申请号：US09987001

申请日：2001-11-13

申请人： Yoshinori Odake ,  Fumihiko Noro ,  Takahiko Hashidzume

发明人： Yoshinori Odake ,  Fumihiko Noro ,  Takahiko Hashidzume

IPC分类号： H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/423

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324

摘要： A gate structure composed of a tunnel insulation film, a floating gate electrode, a capacitive insulation film and a control gate electrode is formed on a semiconductor substrate. Then, ion injection adjustment films that are in contact with the floating gate electrode at least on the side surfaces of the floating gate electrode are formed. After injecting impurity ions into the active region beside the gate structure in the semiconductor substrate while using the gate structure and the ion injection adjustment film as masks, the injected impurity ions are diffused thermally by performing heat treatment on the active region. Film thickness of the ion injection adjustment film is selected to a value to prevent the impurity ions from being injected into the tunnel insulation film and allows the impurity ions to reach lower portions of side end of the floating gate electrode in the active region as a result of diffusive scattering of impurity ions in the semiconductor substrate.

摘要翻译： 在半导体衬底上形成由隧道绝缘膜，浮栅电极，电容绝缘膜和控制栅电极构成的栅极结构。 然后，形成至少在浮栅电极的侧面与浮栅电极接触的离子注入调节膜。 在使用栅极结构和离子注入调节膜作为掩模的同时，在半导体衬底中的栅极结构旁边的有源区域中注入杂质离子之后，通过对活性区域进行热处理，注入的杂质离子被热扩散。 选择离子注入调节膜的膜厚为防止杂质离子注入到隧道绝缘膜中的值，从而允许杂质离子到达活性区域中的浮栅电极的侧端的下部，结果 在半导体衬底中杂质离子的漫射散射。