公开(公告)号：US07229875B2

公开(公告)日：2007-06-12

申请号：US10688077

申请日：2003-10-16

申请人： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

发明人： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

IPC分类号： H01L21/8234

CPC分类号： H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

摘要翻译： 本发明的实施例包括具有高电容且具有改进的可制造性的MIM电容器。 这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。 可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。 将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

公开(公告)号：US20070184610A1

公开(公告)日：2007-08-09

申请号：US11733711

申请日：2007-04-10

申请人： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

发明人： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

IPC分类号： H01L21/8242 ,  H01L21/20

CPC分类号： H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

公开(公告)号：US20060024948A1

公开(公告)日：2006-02-02

申请号：US11157363

申请日：2005-06-21

申请人： Hyeok-sang Oh ,  Ju-hyuck Chung ,  Il-goo Kim

发明人： Hyeok-sang Oh ,  Ju-hyuck Chung ,  Il-goo Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807

摘要： In a method of fabricating a dual damascene interconnection, a reliable trench profile is secured. The method includes forming a lower interconnect feature on a substrate, forming a dielectric layer on the lower interconnect feature, forming a hard mask on the dielectric layer, forming a via in the dielectric layer using the hard mask as an etch mask, forming a trench hard mask defining a trench by patterning the hard mask, forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask, removing the trench hard mask using wet etch, and forming an upper interconnection line by filling the trench and the via with an interconnection material.

摘要翻译： 在制造双镶嵌互连的方法中，确保可靠的沟槽轮廓。 该方法包括在衬底上形成下部互连特征，在下互连特征上形成电介质层，在电介质层上形成硬掩模，使用硬掩模作为蚀刻掩模在电介质层中形成通孔，形成沟槽 硬掩模通过图案化硬掩模来形成沟槽，通过使用沟槽硬掩模作为蚀刻掩模部分地蚀刻介电层，形成与通孔连接并且其中形成上互连线的沟槽，去除沟槽 硬掩模，并且通过用互连材料填充沟槽和通孔来形成上互连线。

公开(公告)号：US07176126B2

公开(公告)日：2007-02-13

申请号：US11157363

申请日：2005-06-21

申请人： Hyeok-sang Oh ,  Ju-hyuck Chung ,  Il-goo Kim

发明人： Hyeok-sang Oh ,  Ju-hyuck Chung ,  Il-goo Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76807

摘要： In a method of fabricating a dual damascene interconnection, a reliable trench profile is secured. The method includes forming a lower interconnect feature on a substrate, forming a dielectric layer on the lower interconnect feature, forming a hard mask on the dielectric layer, forming a via in the dielectric layer using the hard mask as an etch mask, forming a trench hard mask defining a trench by patterning the hard mask, forming a trench, which is connected with the via and in which an upper interconnection line is formed, by partially etching the dielectric layer using the trench hard mask as an etch mask, removing the trench hard mask using wet etch, and forming an upper interconnection line by filling the trench and the via with an interconnection material.

摘要翻译： 在制造双镶嵌互连的方法中，确保可靠的沟槽轮廓。 该方法包括在衬底上形成下部互连特征，在下互连特征上形成电介质层，在电介质层上形成硬掩模，使用硬掩模作为蚀刻掩模在电介质层中形成通孔，形成沟槽 硬掩模通过图案化硬掩模来形成沟槽，通过使用沟槽硬掩模作为蚀刻掩模部分地蚀刻介电层，形成与通孔连接并且其中形成上互连线的沟槽，去除沟槽 硬掩模，并且通过用互连材料填充沟槽和通孔来形成上互连线。