公开(公告)号：US07229875B2

公开(公告)日：2007-06-12

申请号：US10688077

申请日：2003-10-16

Applicant: Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

Inventor： Kyoung-woo Lee ,  Wan-jae Park ,  Jeong-hoon Ahn ,  Kyung-tae Lee ,  Mu-kyeng Jung ,  Yong-jun Lee ,  Il-goo Kim ,  Soo-geun Lee

IPC: H01L21/8234

CPC classification number: H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention include a MIM capacitor having a high capacitance with improved manufacturability. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract translation: 本发明的实施例包括具有高电容且具有改进的可制造性的MIM电容器。 这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。 可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。 将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

公开(公告)号：US20070072319A1

公开(公告)日：2007-03-29

申请号：US11559317

申请日：2006-11-13

Applicant: Jeong-Hoon AHN ,  Kyungtae LEE ,  Mu-Kyung JUNG ,  Yong-Jun LEE

Inventor： Jeong-Hoon AHN ,  Kyungtae LEE ,  Mu-Kyung JUNG ,  Yong-Jun LEE

IPC: H01L21/66 ,  H01L21/331 ,  G01R31/26

CPC classification number: H01L28/55 ,  H01L21/76895 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/1085 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract translation: 本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。 这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。 可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。 将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

公开(公告)号：US20060163701A1

公开(公告)日：2006-07-27

申请号：US11335359

申请日：2006-01-19

Applicant: Jeong-Hoon Ahn ,  Heon-Jong Shin

Inventor： Jeong-Hoon Ahn ,  Heon-Jong Shin

IPC: H01L23/544

CPC classification number: H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

Abstract: Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the semiconductor substrate as part of post-fabrication processing. A representative method according to this invention comprises the sequential steps of: forming a lower layer on a semiconductor substrate; forming a molding layer on the lower layer such that the molding layer includes at least one protective contact hole; subsequently forming a dielectric layer and an upper layer on the molding layer so as to fill the protective contact hole, such dielectric layer being formed of a material having a greater mechanical intensity than that of the molding layer; and then forming protective layer patterns on the upper layer.

Abstract translation: 提供了在半导体衬底的表面上形成这种划线结构的划线结构和方法。 通过本发明的划线结构和方法，作为后制造处理的一部分，在半导体衬底上的切割过程中执行切割过程期间，半导体衬底的物理冲击和开裂倾向可以最小化。 根据本发明的代表性方法包括以下顺序步骤：在半导体衬底上形成下层; 在所述下层上形成模塑层，使得所述模制层包括至少一个保护性接触孔; 随后在成型层上形成电介质层和上层以便填充保护接触孔，这种电介质层由具有比模塑层的机械强度更大的机械强度的材料形成; 然后在上层形成保护层图案。

公开(公告)号：US09087803B2

公开(公告)日：2015-07-21

申请号：US13300274

申请日：2011-11-18

Applicant: Jeong-Hoon Ahn ,  Hyun-Min Choi ,  Oluwafemi O. Ogunsola

Inventor： Jeong-Hoon Ahn ,  Hyun-Min Choi ,  Oluwafemi O. Ogunsola

IPC: H01L21/66 ,  H01L23/525

CPC classification number: H01L22/34 ,  H01L22/14 ,  H01L22/20 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods of fabricating integrated circuit devices utilize fuse elements to support sequential testing of vertically-integrated test elements during fabrication. These methods include forming a first test element, a first fuse and a first test pad electrically connected by the first fuse to the first test element, on a substrate. The first test element is tested by passing a first current between the first test element and first test pad and through the first fuse. The first fuse is then “cut” by increasing an impedance of the first fuse, which may include breaking the first fuse to create an electrical “open” (infinite impedance) or greatly increasing a resistance of the first fuse (e.g., by narrowing the fuse through electromigration). A second test element and a second test pad, which is electrically connected to the second test element and the first test pad, are then formed on the substrate.

Abstract translation: 制造集成电路器件的方法利用熔丝元件来支持制造过程中垂直集成的测试元件的顺序测试。 这些方法包括在衬底上形成第一测试元件，第一熔丝和通过第一熔丝电连接到第一测试元件的第一测试焊盘。 通过在第一测试元件和第一测试焊盘之间传递第一电流并通过第一熔丝来测试第一测试元件。 然后通过增加第一熔丝的阻抗来将第一熔丝“切割”，其可以包括断开第一熔丝以产生电“开放”（无限阻抗）或大大增加第一熔丝的电阻（例如，通过使第 通过电迁移保险丝）。 然后在基板上形成第二测试元件和与第二测试元件和第一测试焊盘电连接的第二测试焊盘。

公开(公告)号：US08013455B2

公开(公告)日：2011-09-06

申请号：US11892318

申请日：2007-08-22

Applicant: Jeong-Hoon Ahn ,  Heon-Jong Shin ,  Sung-Hoon Lee

Inventor： Jeong-Hoon Ahn ,  Heon-Jong Shin ,  Sung-Hoon Lee

IPC: H01L23/488

CPC classification number: H01L24/05 ,  H01L24/06 ,  H01L2224/05093 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/19041 ,  H01L2924/19043

Abstract: A semiconductor device having pads is provided. The semiconductor device includes first pads formed along a first row, and second pads formed along a second row. The first via contact portions extending from the first pads toward the second row, and second via contact portions extending from the second pads toward the first row. The first and second via contact portions are arranged along a third row between the first and second rows.

Abstract translation: 提供具有焊盘的半导体器件。 半导体器件包括沿着第一行形成的第一焊盘，以及沿着第二行形成的第二焊盘。 第一通孔接触部分从第一焊盘朝向第二行延伸，以及第二通孔接触部分，从第二焊盘向第一行延伸。 第一和第二通孔接触部分沿着第一和第二行之间的第三行布置。

公开(公告)号：US07560332B2

公开(公告)日：2009-07-14

申请号：US11733711

申请日：2007-04-10

Applicant: Kyoung-Woo Lee ,  Wan-Jae Park ,  Jeong-Hoon Ahn ,  Kyung-Tae Lee ,  Mu-Kyeng Jung ,  Yong-Jun Lee ,  Il-Goo Kim ,  Soo-Geun Lee

Inventor： Kyoung-Woo Lee ,  Wan-Jae Park ,  Jeong-Hoon Ahn ,  Kyung-Tae Lee ,  Mu-Kyeng Jung ,  Yong-Jun Lee ,  Il-Goo Kim ,  Soo-Geun Lee

IPC: H01L21/8234

CPC classification number: H01L28/40 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the invention include a MIM capacitor that has a high capacitance that can be manufactured without the problems that affected the prior art. Such a capacitor includes an upper electrode, a lower electrode, and a dielectric layer that is intermediate the upper and the lower electrodes. A first voltage can be applied to the upper electrode and a second voltage, which is different from the first voltage, can be applied to the lower electrode. A wire layer, through which the first voltage is applied to the upper electrode, is located in the same level as or in a lower level than the lower electrode.

Abstract translation: 本发明的实施例包括具有高电容的MIM电容器，其可以在没有影响现有技术的问题的情况下被制造。 这种电容器包括上电极，下电极和位于上电极和下电极之间的电介质层。 可以将第一电压施加到上电极，并且可以将不同于第一电压的第二电压施加到下电极。 将第一电压施加到上电极的线层位于与下电极相同的水平或比下电极低的水平位置。

公开(公告)号：US07417302B2

公开(公告)日：2008-08-26

申请号：US11174864

申请日：2005-07-05

Applicant: Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

Inventor： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

IPC: H01L29/00

CPC classification number: H01L23/5223 ,  H01L21/76808 ,  H01L21/76877 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

Abstract translation: 在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。 沿着第一开口的内轮廓形成下电极。 第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有台阶部分的第一开口。 在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。 在电介质层上形成上电极。 因此，抑制了下电极和上电极之间的漏电流。

公开(公告)号：US07358155B2

公开(公告)日：2008-04-15

申请号：US11335359

申请日：2006-01-19

Applicant: Jeong-Hoon Ahn ,  Heon-Jong Shin

Inventor： Jeong-Hoon Ahn ,  Heon-Jong Shin

IPC: H01L21/00

CPC classification number: H01L23/3192 ,  H01L23/562 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/3025 ,  H01L2924/00

Abstract: Scribe-line structures and methods of forming such scribe-line structures on a face of a semiconductor substrate are provided. By means of the scribe-line structures and the methods of this invention, physical shock and cracking tendencies along a semiconductor substrate can be minimized during performance of a cutting process on the semiconductor substrate as part of post-fabrication processing. A representative method according to this invention comprises the sequential steps of: forming a lower layer on a semiconductor substrate; forming a molding layer on the lower layer such that the molding layer includes at least one protective contact hole; subsequently forming a dielectric layer and an upper layer on the molding layer so as to fill the protective contact hole, such dielectric layer being formed of a material having a greater mechanical intensity than that of the molding layer; and then forming protective layer patterns on the upper layer.

Abstract translation: 提供了在半导体衬底的表面上形成这种划线结构的划线结构和方法。 通过本发明的划线结构和方法，作为后制造处理的一部分，在半导体衬底上的切割过程的执行过程中，半导体衬底的物理冲击和开裂倾向可以最小化。 根据本发明的代表性方法包括以下顺序步骤：在半导体衬底上形成下层; 在所述下层上形成模塑层，使得所述模制层包括至少一个保护性接触孔; 随后在成型层上形成电介质层和上层以便填充保护接触孔，这种电介质层由具有比模塑层的机械强度更大的机械强度的材料形成; 然后在上层形成保护层图案。

公开(公告)号：US07351653B2

公开(公告)日：2008-04-01

申请号：US11498888

申请日：2006-08-03

Applicant: Jeong-Hoon Ahn ,  Kyung-Tae Lee ,  Yoon-Hae Kim

Inventor： Jeong-Hoon Ahn ,  Kyung-Tae Lee ,  Yoon-Hae Kim

IPC: H01L21/4763

CPC classification number: H01L21/76822 ,  H01L21/7684

Abstract: Disclosed are methods for carrying out a damascene process in semiconductor fabrication including the steps of: forming an intermetal dielectric film on a semiconductor substrate; patterning the intermetal dielectric film and forming an intermetal dielectric pattern comprising at least two layers of different chemical compositions that includes at least an opening penetrating the intermetal dielectric film; forming a conductive film to fill the opening on the intermetal dielectric pattern; and etching the conductive film by means of a chemical/mechanical polishing operation until exposing an upper face of the intermetal dielectric pattern and the top of the filled opening so as to form a conductive pattern. An etching process is then performed to selectively remove an upper portion of the intermetal dielectric pattern. Because the intermetal dielectric film is variable in chemical composition according to different constituent layers, the upper portion of the intermetal dielectric pattern can be selectively removed by using a chemical etching composition that demonstrates etching selectivity relative to the different layers of the intermetal dielectric film.

Abstract translation: 公开了用于在半导体制造中执行镶嵌工艺的方法，包括以下步骤：在半导体衬底上形成金属间电介质膜; 图案化金属间电介质膜并形成包括至少两层不同化学组成的金属间电介质图案，其包括至少穿过金属间电介质膜的开口; 形成导电膜以填充金属间电介质图案上的开口; 并通过化学/机械抛光操作蚀刻导电膜，直到暴露金属间电介质图案的上表面和填充开口的顶部，以形成导电图案。 然后执行蚀刻处理以选择性地去除金属间电介质图案的上部。 由于金属间电介质膜根据不同的构成层的化学组成是可变的，所以可以通过使用相对于金属间电介质膜的不同层表现出蚀刻选择性的化学蚀刻组合物来选择性地去除金属间电介质图案的上部。

公开(公告)号：US20050029010A1

公开(公告)日：2005-02-10

申请号：US10891062

申请日：2004-07-15

Applicant: Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

Inventor： Jeong-hoon Ahn ,  Hyo-jong Lee ,  Kyung-tae Lee ,  Kyoung-woo Lee ,  Soo-geun Lee ,  Bong-seok Suh

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L23/52 ,  H05K1/11

CPC classification number: H01L21/76877 ,  H01L21/76847

Abstract: A metal interconnection structure includes a lower metal interconnection layer disposed in a first inter-layer dielectric layer. An inter-metal dielectric layer having a via contact hole that exposes a portion of surface of the lower metal layer pattern is disposed on the first inter-layer dielectric layer and the lower metal layer pattern. A second inter-layer dielectric layer having a trench that exposes the via contact hole is formed on the inter-metal dielectric layer. A barrier metal layer is formed on a vertical surface of the via contact and the exposed surface of the second lower metal interconnection layer pattern. A first upper metal interconnection layer pattern is disposed on the barrier metal layer, thereby filling the via contact hole and a portion of the trench. A void diffusion barrier layer is disposed on the first metal interconnection layer pattern and a second upper metal interconnection layer pattern is disposed on the void diffusion barrier layer to completely fill the trench.

Abstract translation: 金属互连结构包括设置在第一层间电介质层中的下金属互连层。 具有暴露下部金属层图案的一部分表面的通孔接触孔的金属间介电层设置在第一层间电介质层和下部金属层图案上。 在金属间电介质层上形成具有暴露通孔接触孔的沟槽的第二层间电介质层。 在通孔接触件的垂直表面和第二下部金属互连层图案的暴露表面上形成阻挡金属层。 第一上金属互连层图案设置在阻挡金属层上，从而填充通孔接触孔和沟槽的一部分。 空隙扩散阻挡层设置在第一金属互连层图案上，并且第二上金属互连层图案设置在空隙扩散阻挡层上以完全填充沟槽。