公开(公告)号：US06204122B1

公开(公告)日：2001-03-20

申请号：US08932641

申请日：1997-09-17

申请人： Kyung-joong Joo ,  Jeong-hyuk Choi ,  Wang-chul Shin

发明人： Kyung-joong Joo ,  Jeong-hyuk Choi ,  Wang-chul Shin

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/42324

摘要： Methods of forming nonvolatile integrated circuit memory devices having high capacitive coupling ratios include the steps of forming a tunneling oxide layer on a face of a semiconductor substrate and then forming a forming a first conductive layer (e.g., doped polysilicon) on the tunneling oxide layer. A floating gate electrode mask is then patterned on the first conductive layer so as to expose a portion the first conductive layer. A second conductive layer is then patterned on the exposed portion of the first conductive layer and on sidewalls of the floating gate electrode mask, to define a concave or U-shaped floating gate electrode having conductive sidewall extensions. The sidewall extensions increase the effective area of the floating gate electrode and increase the capacitance coupling ratio which enables programming and erasing at reduced voltage levels. A first electrically insulating layer is then formed on the U-shaped floating gate electrode, opposite the tunneling oxide layer. A control gate is then formed on the first electrically insulating layer, opposite the U-shaped floating gate electrode.

摘要翻译： 形成具有高电容耦合比的非易失性集成电路存储器件的方法包括以下步骤：在半导体衬底的表面上形成隧穿氧化物层，然后在隧道氧化物层上形成第一导电层（例如掺杂多晶硅）。 然后在第一导电层上图案化浮栅电极掩模，以暴露第一导电层的一部分。 然后在第一导电层的暴露部分和浮栅电极掩模的侧壁上将第二导电层图案化，以限定具有导电侧壁延伸部的凹形或U形浮栅。 侧壁延伸增加了浮栅电极的有效面积并增加了电容耦合比，这使得能够在降低的电压电平下进行编程和擦除。 然后在U形浮栅上形成第一电绝缘层，与隧道氧化物层相对。 然后在与U形浮栅相对的第一电绝缘层上形成控制栅。

公开(公告)号：US06483749B1

公开(公告)日：2002-11-19

申请号：US09650493

申请日：2000-08-29

申请人： Jeong-hyuk Choi ,  Yong-ju Choi ,  Kyung-joong Joo ,  Keon-soo Kim

发明人： Jeong-hyuk Choi ,  Yong-ju Choi ,  Kyung-joong Joo ,  Keon-soo Kim

IPC分类号： G11C1604

CPC分类号： H01L27/11526 ,  G11C16/0416 ,  H01L27/11521 ,  H01L27/11536

摘要： A non-volatile memory device including a cell array region formed having a plurality of parallel bit lines, a plurality of parallel word lines, a plurality of memory cells, and a plurality of common source lines, the plurality of bit lines being orthogonal to the plurality of word lines, each of the memory cells being connected to a bit line and a word line and having a stacked gate comprised of a floating gate and a control gate and a source/drain region, the plurality of common source lines being parallel to the plurality of bit lines. The non-volatile memory device also includes a peripheral circuit region for driving the memory cells in the cell array region is formed. The cell array region includes one or more bulk bias contact structures for maintaining the voltage of a bulk region in which the cell array region is formed, at or below a predetermined voltage. The non-volatile memory device can uniformly maintain the voltage of a bulk region regardless of the position of memory cells without increasing the area of a cell array.

摘要翻译： 一种非易失性存储器件，包括形成有多个并行位线，多个并行字线，多个存储器单元和多个公共源极线的单元阵列区域，所述多个位线正交于 多个字线，每个存储器单元连接到位线和字线，并且具有由浮置栅极和控制栅极以及源极/漏极区域构成的堆叠栅极，所述多个公共源极线平行于 多个位线。 非易失性存储器件还包括用于驱动单元阵列区域中的存储单元的外围电路区域。 电池阵列区域包括一个或多个体积偏置接触结构，用于维持其中形成电池阵列区域的体区的电压，等于或低于预定电压。 无论存储器单元的位置如何，非易失性存储器件均可均匀地保持体区的电压，而不增加单元阵列的面积。

公开(公告)号：US06121115A

公开(公告)日：2000-09-19

申请号：US135246

申请日：1998-08-17

申请人： Kyung-joong Joo ,  Jeong-hyuk Choi

发明人： Kyung-joong Joo ,  Jeong-hyuk Choi

IPC分类号： H01L21/10 ,  H01L21/76 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L29/1033

摘要： An integrated circuit memory device includes a semiconductor substrate having a memory cell area and a select transistor area. A first field insulation layer is included in the memory cell area, and a first channel stop impurity layer is included beneath the first field insulation layer. The first channel stop impurity layer is narrower than the first field insulation area. A second field insulation layer is included in the select transistor area, and a second channel stop impurity layer is included beneath the second field insulation layer. The second channel stop impurity layer is wider than the second field insulation layer. Integrated circuit memory devices are fabricated by defining a memory cell area and a select transistor area of a semiconductor substrate. The memory cell area includes a memory cell active area and a memory cell field area. The select transistor area includes a select transistor active area and a select transistor field area. First channel stop impurity ions are implanted into the select transistor field area. A first field insulation layer is formed in the memory cell field area, and a second field insulation layer is formed in the select transistor field area, such that the first channel stop impurity ions lie beneath the second field insulation area. Second channel stop impurity ions are implanted through the central portion of the first field insulation area, such that the second channel stop impurity ions lie beneath the central portion of the first field insulation layer.

摘要翻译： 集成电路存储器件包括具有存储单元区域和选择晶体管区域的半导体衬底。 第一场绝缘层包括在存储单元区域中，第一场绝缘层下方包括第一沟道截止杂质层。 第一通道阻挡杂质层比第一场绝缘区域窄。 第二场绝缘层包括在选择晶体管区域中，第二沟道截止杂质层包含在第二场绝缘层下面。 第二通道阻挡杂质层比第二场绝缘层宽。 通过限定半导体衬底的存储单元区域和选择晶体管区域来制造集成电路存储器件。 存储单元区域包括存储单元有效区和存储单元场区。 选择晶体管区域包括选择晶体管有源区和选择晶体管场区。 第一通道停止杂质离子注入选择晶体管场区域。 第一场绝缘层形成在存储单元场区中，第二场绝缘层形成在选择晶体管场区中，使得第一沟道阻止杂质离子位于第二场隔离区之下。 第二通道阻止杂质离子通过第一场绝缘区域的中心部分注入，使得第二通道阻止杂质离子位于第一场绝缘层的中心部分的下方。

公开(公告)号：US5841163A

公开(公告)日：1998-11-24

申请号：US701627

申请日：1996-08-22

申请人： Kyung-joong Joo ,  Jeong-hyuk Choi

发明人： Kyung-joong Joo ,  Jeong-hyuk Choi

IPC分类号： H01L21/10 ,  H01L21/76 ,  H01L21/8247 ,  H01L27/08 ,  H01L27/115 ,  H01L29/10 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L27/11519 ,  H01L27/11521 ,  H01L29/1033

摘要： An integrated circuit memory device includes a semiconductor substrate having a memory cell area and a select transistor area. A first field insulation layer is included in the memory cell area, and a first channel stop impurity layer is included beneath the first field insulation layer. The first channel stop impurity layer is narrower than the first field insulation area. A second field insulation layer is included in the select transistor area, and a second channel stop impurity layer is included beneath the second field insulation layer. The second channel stop impurity layer is wider than the second field insulation layer. Integrated circuit memory devices are fabricated by defining a memory cell area and a select transistor area of a semiconductor substrate. The memory cell area includes a memory cell active area and a memory cell field area. The select transistor area includes a select transistor active area and a select transistor field area. First channel stop impurity ions are implanted into the select transistor field area. A first field insulation layer is formed in the memory cell field area, and a second field insulation layer is formed in the select transistor field area, such that the first channel stop impurity ions lie beneath the second field insulation area. Second channel stop impurity ions are implanted through the central portion of the first field insulation area, such that the second channel stop impurity ions lie beneath the central portion of the first field insulation layer.

摘要翻译： 集成电路存储器件包括具有存储单元区域和选择晶体管区域的半导体衬底。 第一场绝缘层包括在存储单元区域中，第一场绝缘层下方包括第一沟道截止杂质层。 第一通道阻挡杂质层比第一场绝缘区域窄。 第二场绝缘层包括在选择晶体管区域中，第二沟道截止杂质层包含在第二场绝缘层下面。 第二通道阻挡杂质层比第二场绝缘层宽。 通过限定半导体衬底的存储单元区域和选择晶体管区域来制造集成电路存储器件。 存储单元区域包括存储单元有效区和存储单元场区。 选择晶体管区域包括选择晶体管有源区和选择晶体管场区。 第一通道停止杂质离子注入选择晶体管场区域。 第一场绝缘层形成在存储单元场区中，第二场绝缘层形成在选择晶体管场区中，使得第一沟道阻止杂质离子位于第二场隔离区之下。 第二通道阻止杂质离子通过第一场绝缘区域的中心部分注入，使得第二通道阻止杂质离子位于第一场绝缘层的中心部分的下方。