公开(公告)号：US09997588B2

公开(公告)日：2018-06-12

申请号：US15479645

申请日：2017-04-05

Applicant: LG DISPLAY CO., LTD.

Inventor： Seung-Won Jung ,  Dong-Sun Kim ,  Won-Joon Ho

IPC: H01L23/48 ,  H01L27/32 ,  H01L51/00 ,  H01L51/52

CPC classification number: H01L27/3276 ,  H01L27/3272 ,  H01L51/0096 ,  H01L51/5253

Abstract: A display device according to an embodiment includes a display panel and a circuit board connected to the display panel. The circuit board is connected to a bonding area of the display panel by an anisotropic conductive film. The display panel includes a cover insulating layer exposing the bonding area. The cover insulating layer includes at least one trench crossing an edge area, which is located outside the bonding area.

公开(公告)号：US10043679B2

公开(公告)日：2018-08-07

申请号：US15464548

申请日：2017-03-21

Applicant: LG DISPLAY CO., LTD.

Inventor： Hee-Jung Yang ,  Hyung-Tae Kim ,  Jae-Young Jeong ,  Gyu-Won Han ,  Dong-Sun Kim ,  Won-Joon Ho

IPC: H01L21/428 ,  H01L29/66 ,  H01L27/12 ,  H01L29/786 ,  H01L29/08 ,  H01L21/4757

Abstract: A method of fabricating an array substrate including forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by irradiating X-rays or UV rays to the oxide semiconductor layer exposed outside the gate electrode; forming an inter insulating layer on the gate electrode and having first contact holes that expose the source and drain areas; and forming source and drain electrodes on the inter insulating layer and contacting the source and drain areas through the first contact holes, respectively.

公开(公告)号：US09276016B2

公开(公告)日：2016-03-01

申请号：US14542909

申请日：2014-11-17

Applicant: LG Display Co., Ltd.

Inventor： Hee-Jung Yang ,  Dong-Sun Kim ,  Won-Joon Ho ,  A-Ra Kim

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/49 ,  H01L21/28

CPC classification number: H01L27/124 ,  H01L21/28008 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/7869 ,  H01L29/78696

Abstract: An array substrate including: a gate barrier layer on a substrate; a gate line on the gate barrier layer, the gate line having a gate open portion exposing the gate barrier layer in a gate electrode region; a gate insulating layer on the gate line; an active layer on the gate insulating layer over the gate barrier layer in the gate electrode region; and source and drain electrodes spaced apart from each other on the active layer.

Abstract translation: 一种阵列基板，包括：基板上的栅极阻挡层; 栅极栅极层上的栅极线，栅极线具有在栅电极区域中暴露栅极势垒层的栅极开口部分; 栅极线上的栅极绝缘层; 位于栅电极区域上的栅极阻挡层上的栅绝缘层上的有源层; 以及在有源层上彼此间隔开的源极和漏极。

公开(公告)号：US09640567B2

公开(公告)日：2017-05-02

申请号：US15040605

申请日：2016-02-10

Applicant: LG DISPLAY CO., LTD.

Inventor： Hee-Jung Yang ,  Hyung-Tae Kim ,  Jae-Young Jeong ,  Gyu-Won Han ,  Dong-Sun Kim ,  Won-Joon Ho

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/428 ,  H01L21/4757 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/0847 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method of fabrication an array substrate which includes foaming an oxide semiconductor layer on a substrate; forming a gate insulating layer corresponding to a central portion of the oxide semiconductor layer; forming a first reactive metallic pattern and second reactive metallic patterns on the gate insulating layer and portions of the oxide semiconductor layer exposed outside the gate insulating layer, respectively; forming a gate electrode on the first reactive metallic pattern; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing heat treatment such that materials of the second reactive metallic patterns are diffused into the oxide semiconductor layer contacting the second reactive metallic patterns; forming an inter insulating layer on the gate electrode and having first contact holes that expose the second reactive metallic patterns; and forming source and drain electrodes on the inter insulating layer and contacting the second reactive metallic patterns through the first contact holes, respectively.

公开(公告)号：US09293478B2

公开(公告)日：2016-03-22

申请号：US14061563

申请日：2013-10-23

Applicant: LG DISPLAY CO., LTD.

Inventor： Hee-Jung Yang ,  Hyung-Tae Kim ,  Jae-Young Jeong ,  Gyu-Won Han ,  Dong-Sun Kim ,  Won-Joon Ho

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L21/428 ,  H01L21/4757 ,  H01L27/1225 ,  H01L27/1262 ,  H01L29/0847 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method of fabrication an array substrate includes forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing hydrogen plasma treatment; forming barrier layers on the source and drain areas, the barrier layer having a first thickness; forming an inter insulating layer on the gate electrode and having first contact holes that expose the barrier layers; and forming source and drain electrodes on the inter insulating layer and contacting the barrier layers through the first contact holes, respectively.

Abstract translation: 制造阵列基板的方法包括在基板上形成氧化物半导体层; 顺序地形成对应于氧化物半导体层的中心部分的栅极绝缘层和栅电极; 通过进行氢等离子体处理在所述氧化物半导体层中形成具有导电性质的源区和漏区; 在源极和漏极区域上形成阻挡层，阻挡层具有第一厚度; 在所述栅电极上形成绝缘层，并具有暴露所述阻挡层的第一接触孔; 以及在所述绝缘层上形成源电极和漏电极，并且分别通过所述第一接触孔与所述阻挡层接触。