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    DISPLAY DEVICE AND DRIVING METHOD THEREOF
    1.
    发明申请
    DISPLAY DEVICE AND DRIVING METHOD THEREOF 有权
    显示装置及其驱动方法

    公开(公告)号：US20160189631A1

    公开(公告)日：2016-06-30

    申请号：US14973043

    申请日：2015-12-17

    Applicant: LG DISPLAY CO., LTD.

    Inventor： Jungjae KIM ,  Jaewon Han

    IPC: G09G3/32

    CPC classification number: G09G3/3291 ,  G09G3/3225 ,  G09G3/3266 ,  G09G2310/0278 ,  G09G2320/0209 ,  G09G2320/0223 ,  G09G2320/0233 ,  G09G2330/025 ,  G09G2330/028 ,  G09G2360/16

    Abstract: Provided is a display device that includes, for example, a display panel, a driver, a power supply unit, and a timing controller. The power supply unit may supply a voltage to the driver. The power supply unit may perform a compensation operation to vary an output voltage output from the power supply unit itself to correspond to a variation of a load before the load varies.

    Abstract translation: 提供了一种显示装置，其包括例如显示面板，驱动器，电源单元和定时控制器。 电源单元可以向驱动器提供电压。 电源单元可以执行补偿操作以改变从电源单元本身输出的输出电压，以对应于负载变化之前的负载变化。

    Gate clock generator and display device having the same
    2.
    发明授权
    Gate clock generator and display device having the same 有权

    公开(公告)号：US10810946B2

    公开(公告)日：2020-10-20

    申请号：US16503050

    申请日：2019-07-03

    Applicant: LG Display Co., Ltd.

    Inventor： Jaewon Han ,  Soondong Cho ,  Jungjae Kim ,  Sanguk Lee ,  Hyungjin Choe

    IPC: G09G3/3266 ,  G09G3/3291

    Abstract: The present disclosure provides a gate clock generator including a counter, a buffer control signal generator, and an output unit. The counter receives control data having rising timing information and falling timing information and a main clock. The counter generates a first output when a value is obtained by counting the main clock from a preset reference time point reaches rising data. The counter further generates a second output when a value is obtained by counting the main clock from the reference time point reaches falling data. The buffer control signal generator generates a first buffer control signal of a gate ON voltage from a timing of the first output to a timing of the second output. The output unit outputs a gate ON voltage of a gate clock during an output period of the gate ON voltage of the first buffer control signal.

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