公开(公告)号：US08716062B1

公开(公告)日：2014-05-06

申请号：US14146937

申请日：2014-01-03

Applicant: LG Display Co., Ltd.

Inventor： Chang-Il Ryoo ,  Hyun-Sik Seo ,  Jong-Uk Bae

IPC: H01L21/00

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method of fabricating an array substrate and a display device including the array substrate are discussed. According to an embodiment, the array substrate includes a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an oxide semiconductor layer and an etch prevention layer formed on the gate insulating layer, wherein ends of the oxide semiconductor layer and ends of the etch prevention layer are aligned with each other; source and drain electrodes formed on the etch prevention layer; a passivation layer including a contact hole formed on the source and drain electrodes and on the gate insulating layer; and a pixel electrode formed on the passivation layer and through the contact hole.

Abstract translation: 讨论了制造阵列基板的方法和包括阵列基板的显示装置。 根据实施例，阵列基板包括形成在基板上的栅电极; 形成在所述栅电极上的栅极绝缘层; 形成在栅绝缘层上的氧化物半导体层和防蚀层，其中氧化物半导体层的端部和防蚀层的端部彼此对准; 源极和漏极形成在防蚀层上; 钝化层，包括形成在源电极和漏电极上以及栅极绝缘层上的接触孔; 以及形成在钝化层上并通过接触孔的像素电极。

公开(公告)号：US08659017B2

公开(公告)日：2014-02-25

申请号：US13923019

申请日：2013-06-20

Applicant: LG Display Co., Ltd.

Inventor： Chang-Il Ryoo ,  Hyun-Sik Seo ,  Jong-Uk Bae

IPC: H01L29/10

CPC classification number: H01L27/1288 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/127 ,  H01L29/66969 ,  H01L29/7869

Abstract: A method of fabricating an array substrate and a display device including the array substrate are discussed. According to an embodiment, the array substrate includes a gate electrode formed on a substrate; a gate insulating layer formed on the gate electrode; an oxide semiconductor layer and an etch prevention layer formed on the gate insulating layer, wherein ends of the oxide semiconductor layer and ends of the etch prevention layer are aligned with each other; source and drain electrodes formed on the etch prevention layer; a passivation layer including a contact hole formed on the source and drain electrodes and on the gate insulating layer; and a pixel electrode formed on the passivation layer and through the contact hole.