公开(公告)号：US09824771B2

公开(公告)日：2017-11-21

申请号：US14133243

申请日：2013-12-18

Applicant: LG DISPLAY CO., LTD.

Inventor： Sunghyun Cho ,  Chungsik Kong ,  Sungwook Chang

IPC: G11C19/00 ,  G11C19/28

CPC classification number: G11C19/28 ,  G09G2310/0286

Abstract: Provided is a gate shift register including a plurality of stages receiving a plurality of clocks to generate gate output signals, in which an n-th stage of the stages dependently connected to each other includes an output node outputting an n-th gate output signal, a pull-up TFT switching a current flow between an input terminal of a clock having an n-th phase and the output node according to a potential of a Q node, a pull-down TFT switching the current flow between an input terminal of a low potential voltage and the output node according to a potential of a QB node, appnd a BTS compensation unit periodically discharging the QB node at a low potential level just after the n-th stage is reset and just until the n-th stage is set in a next frame.

公开(公告)号：US09754551B2

公开(公告)日：2017-09-05

申请号：US14953614

申请日：2015-11-30

Applicant: LG Display Co., Ltd.

Inventor： Hun Jeoung ,  Sanghee Yu ,  Sunghyun Cho ,  Bosun Lee ,  Byoungwoo Kim ,  Sungwook Chang

IPC: G09G3/36 ,  G09G5/00 ,  G11C19/28

CPC classification number: G09G5/003 ,  G09G3/3677 ,  G09G3/3696 ,  G09G2310/0251 ,  G09G2310/0267 ,  G09G2310/0275 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/063 ,  G09G2310/08 ,  G09G2320/0257 ,  G09G2330/027 ,  G09G2330/04 ,  G11C19/28

Abstract: A display panel and a method of driving the same are disclosed. The display panel includes a shift register with a plurality of stages configured to shift and to output a scan pulse for a plurality of scan lines. Each stage includes a pull-up transistor and a pull-down transistor coupled in series and defining an output node therebetween, a driver with a first node coupled to a gate electrode of the pull-up transistor and a second node coupled to a gate electrode of the pull-down transistor; and a node controller coupled to the first node, the second node, and the output node. In each stage, the node controller is configured to selectively apply a reference voltage at the first node and the second node in response to a control signal.