Abstract:
A gate driving circuit and a display device are disclosed. The gate driving circuit includes a shift register including a plurality of stages. Among the stages, an Nth stage includes a first transistor charging a Q node and a junction stress control circuit. A pull-up transistor using the Q node as a gate input controls an output signal of a stage output terminal. The junction stress control circuit includes a first, second, and third control transistors. The first control transistor, the second control transistor, the third control transistor, and the first transistor are connected to each other through a common node. The second control transistor adjusts junction stresses for the first control transistor and the first transistor by controlling a voltage of the common node. When the second control transistor is turned off, the third control transistor discharges the voltage of the common node.
Abstract:
A display panel and a method of driving the same are disclosed. The display panel includes a shift register with a plurality of stages configured to shift and to output a scan pulse for a plurality of scan lines. Each stage includes a pull-up transistor and a pull-down transistor coupled in series and defining an output node therebetween, a driver with a first node coupled to a gate electrode of the pull-up transistor and a second node coupled to a gate electrode of the pull-down transistor; and a node controller coupled to the first node, the second node, and the output node. In each stage, the node controller is configured to selectively apply a reference voltage at the first node and the second node in response to a control signal.
Abstract:
An array substrate includes: a display area; a non-display area outside of the display area; a gate-in-panel (GIP) circuit in the non-display area; a plurality of clock signal lines in the non-display area and configured to transfer signals to the GIP circuit; and connection lines in the non-display area and configured to connect the plurality of clock signal lines to the GIP circuit. Each of the plurality of clock signal lines is a ring shaped line.
Abstract:
Disclosed is a display apparatus in which a gate driving circuit is disposed in each of non-display areas other than a non-display area including a pad part among a plurality of non-display areas, and a plurality of connection lines provided on a layer differing from a plurality of gate lines and connected to the gate lines are provided.
Abstract:
A touch sensor integrated display device includes a plurality of common electrode blocks serving as touch-sensing regions and/or touch-driving regions. Conductive lines connected to the common electrode blocks are placed under the common electrode blocks and the pixel electrodes of the pixels, and they are routed across the active area, directly toward an inactive area where drive-integrated circuits are located. The conductive lines are positioned under one or more planarization layers, and are connected to the corresponding common electrode blocks via one or more contact holes.
Abstract:
A touch display device, a display panel, and a gate driving circuit are disclosed. A touch display device comprises a display panel having subpixels, a gate driving circuit including gate stages for applying a scan signal to the display panel through gate lines and dummy stages selectively disposed between the gate stages, and a touch driving circuit applying a touch driving signal to the display panel through touch lines and receiving a touch sensing signal generated by the display panel, wherein the dummy stages are divided into two or more dummy stage groups, and wherein a group control signal line for applying a group control signal based on dummy stage group and an individual control signal line for applying an individual control signal to each dummy stage included in the dummy stage group are disposed along a bezel area.
Abstract:
A touch sensor integrated display device includes a plurality of common electrode blocks serving as touch-sensing regions and/or touch-driving regions. Conductive lines connected to the common electrode blocks are placed under the common electrode blocks and the pixel electrodes of the pixels, and they are routed across the active area, directly toward an inactive area where drive-integrated circuits are located. The conductive lines are positioned under one or more planarization layers, and are connected to the corresponding common electrode blocks via one or more contact holes.