公开(公告)号：US20020089614A1

公开(公告)日：2002-07-11

申请号：US10028973

申请日：2001-12-28

Applicant: LG.Philips LCD CO., Ltd.

Inventor： Ik Soo Kim

IPC: G02F001/1333

CPC classification number: G02F1/1309 ,  G02F1/1345 ,  G02F2001/136254

Abstract: An LCD device includes a plurality of data pads; an LCD panel defined by a plurality of pad regions; a first shorting bar connected to odd numbered data pads among the plurality of data pads; a second shorting bar connected to even numbered data pads among the plurality of data pads; and a test pad formed in a predetermined portion of a pad region among the plurality of pad regions to apply a signal voltage for on/off testing to the first shorting bar and the second shorting bar.

Abstract translation: LCD装置包括多个数据焊盘; 由多个焊盘区域限定的LCD面板; 连接到所述多个数据焊盘中的奇数数据焊盘的第一短路棒; 连接到所述多个数据焊盘中的偶数数据焊盘的第二短路棒; 以及形成在所述多个焊盘区域中的焊盘区域的预定部分中的测试焊盘，以将用于开/关测试的信号电压施加到所述第一短路棒和所述第二短路棒。

公开(公告)号：US20030096441A1

公开(公告)日：2003-05-22

申请号：US10330126

申请日：2002-12-30

Applicant: LG.Philips LCD Co., LTD

Inventor： Ik Soo Kim

IPC: H01L021/00 ,  H01L021/84 ,  H01L027/12 ,  H01L031/0392 ,  H01L027/01

CPC classification number: H01L29/66765 ,  H01L29/4908

Abstract: A method of fabricating a thin film transistor substrate for an X-ray detector reduces the number of steps in etching processes using masks. In the method, a gate line, a gate pad and a gate electrode of a thin film transistor are simultaneously formed on a certain substrate. A gate insulating layer is entirely coated, and then a semiconductor layer of the thin film transistor is formed. A data pad, a data line, source and drain electrodes of the thin film transistor and a ground electrode are simultaneously formed. An electrode for a charging capacitor is formed, and then an insulating film for the charging capacitor is formed. An electrode for preventing an etching of the insulating film for the charging capacitor is formed. A protective film for protecting the thin film transistor is formed. Contact holes are formed in the protective film. Finally, a pixel electrode is provided. Accordingly, the data pad and the data line are formed of a molybdenum metal and at the same layer, and the molybdenum layers of the data pad and the gate pad are connected to the driver IC chip using the wire bonding technique. As a result, the present method is capable of reducing nine-step mask etching processes in the prior art to a seven-step mask etching processes.

Abstract translation: 制造用于X射线检测器的薄膜晶体管衬底的方法减少了使用掩模的蚀刻工艺中的步骤数。 在该方法中，在一定的衬底上同时形成薄膜晶体管的栅极线，栅极焊盘和栅电极。 完全涂覆栅极绝缘层，然后形成薄膜晶体管的半导体层。 同时形成薄膜晶体管的数据焊盘，数据线，源极和漏极以及接地电极。 形成用于充电电容器的电极，然后形成用于充电电容器的绝缘膜。 形成用于防止用于充电电容器的绝缘膜的蚀刻的电极。 形成用于保护薄膜晶体管的保护膜。 在保护膜中形成接触孔。 最后，提供像素电极。 因此，数据焊盘和数据线由钼金属形成，在相同的层上，数据焊盘和栅极焊盘的钼层使用引线接合技术连接到驱动器IC芯片。 结果，本方法能够将现有技术中的九步掩模蚀刻工艺减少到七步掩模蚀刻工艺。

公开(公告)号：US20030058377A1

公开(公告)日：2003-03-27

申请号：US10133320

申请日：2002-04-29

Applicant: LG.Philips LCD Co., Ltd.

Inventor： Gee Sung Chae ,  Jae Kyun Lee ,  Ik Soo Kim

IPC: G02F001/136

CPC classification number: G02F1/136213 ,  G02F1/133512

Abstract: An array substrate for a liquid crystal display device includes a transparent substrate, a gate line arranged along a first direction on the transparent substrate, a gate electrode extending from the gate line, a common line arranged along the first direction adjacent to the gate line and having a protrusion, a gate insulation layer on the transparent substrate to cover the gate line, the gate electrode, and the common electrode, an active layer on the gate insulation layer and over the gate electrode, first and second ohmic contact layers on the active layer, a data line arranged along a second direction perpendicular to the first upon the gate insulation layer, a source electrode extending from the data line and contacting the first ohmic contact layer, a drain electrode spaced apart from the source electrode and contacting the second ohmic contact layer, a first capacitor electrode formed on the gate insulation layer and connected to the drain electrode, the first capacitor electrode overlapping the common line and the protrusion of the common line, a passivation layer formed on the gate insulation layer to cover the data line, the source and drain electrodes, and the first capacitor electrode, the passivation layer having a first contact hole exposing a portion of the capacitor electrode, and a pixel electrode formed on the passivation layer and contacting the first capacitor electrode through the first contact hole.