ADHESIVE TAPE FOR SEMICONDUCTOR PROCESSING AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

    公开(公告)号:US20180308739A1

    公开(公告)日:2018-10-25

    申请号:US15768652

    申请日:2017-03-02

    Abstract: The pressure sensitive adhesive tape for semiconductor processing of the present invention is a pressure sensitive adhesive tape for semiconductor processing, which, in a step of grinding a back face of a semiconductor wafer having a groove formed on a front face thereof or having a modified region formed therein to singulate the semiconductor wafer into semiconductor chips, is stuck on the front face of the semiconductor wafer and used, the pressure sensitive adhesive tape for semiconductor processing including a base, a buffer layer provided on one face of the base, and a pressure sensitive adhesive layer provided on the other face of the base, and having a ratio (D2/D1) of a thickness (D2) of the buffer layer to a thickness (D1) of the base of 0.7 or less and an indentation depth (X) of the front face on the buffer layer side of 2.5 μm or less.

    ADHESIVE TAPE FOR SEMICONDUCTOR PROCESSING AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE

    公开(公告)号:US20190385889A1

    公开(公告)日:2019-12-19

    申请号:US16558607

    申请日:2019-09-03

    Abstract: The pressure sensitive adhesive tape for semiconductor processing of the present invention is a pressure sensitive adhesive tape for semiconductor processing, which, in a step of grinding a back face of a semiconductor wafer having a groove formed on a front face thereof or having a modified region formed therein to singulate the semiconductor wafer into semiconductor chips, is stuck on the front face of the semiconductor wafer and used, the pressure sensitive adhesive tape for semiconductor processing including a base, a buffer layer provided on one face of the base, and a pressure sensitive adhesive layer provided on the other face of the base, and having a ratio (D2/D1) of a thickness (D2) of the buffer layer to a thickness (D1) of the base of 0.7 or less and an indentation depth (X) of the front face on the buffer layer side of 2.5 μm or less.

    THERMOELECTRIC CONVERSION MODULE
    3.
    发明公开

    公开(公告)号:US20230380288A1

    公开(公告)日:2023-11-23

    申请号:US18034442

    申请日:2021-10-28

    CPC classification number: H10N10/17

    Abstract: Provided is a thin thermoelectric conversion module provided with no support base material and including: an integrated body including an insulator configured to fill a gap defined by a chip of a P-type thermoelectric conversion material and a chip of an N-type thermoelectric conversion material, the chips being alternately arranged and spaced apart from each other; a common first electrode provided on one surface of the integrated body and joining one surface of the chip of the P-type thermoelectric conversion material and one surface of the chip of the N-type thermoelectric conversion material; and a common second electrode provided on another surface of the integrated body, facing the first electrode, and joining another surface of the chip of the N-type thermoelectric conversion material and another surface of the chip of the P-type thermoelectric conversion material, in which the first electrode and the second electrode provide electrically serial connection between the chip of the P-type thermoelectric conversion material and the chip of the N-type thermoelectric conversion material, and both surfaces of the thermoelectric conversion module are provided with no base material.

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