High speed signal drive circuit
    1.
    发明授权

    公开(公告)号:US11108387B2

    公开(公告)日:2021-08-31

    申请号:US16725061

    申请日:2019-12-23

    IPC分类号: H03K17/04 H03K19/20 H03K19/02

    摘要: A high speed signal drive circuit includes a D-PHY drive signal generation module, a C-PHY drive signal generation module, a drive signal selection module and a multiplex drive module. An output terminal of the D-PHY drive signal generation module and an output terminal of the C-PHY drive signal generation module are both connected to an input terminal of the drive signal selection module. An output terminal of the drive signal selection module is connected to an input terminal of the multiplex drive module. The drive signal selection module controls control switches of the multiplex drive module to be on and off based on a D-PHY drive signal or a C-PHY drive signal, so that the multiplex drive module functions as a D-PHY drive circuit or a C-PHY drive circuit. Thus, dual functions of the D-PHY drive circuit and the C-PHY drive circuit can be realized.

    Termination resistor calibration circuit and control method thereof

    公开(公告)号:US10193552B1

    公开(公告)日:2019-01-29

    申请号:US16017373

    申请日:2018-06-25

    IPC分类号: H03K19/00 H03K5/24

    摘要: The termination resistor calibration circuit and a control method thereof are provided. The resistance of the termination resistor of the CML transmitter is directly calibrated, so that the error caused by duplicating the resistor can be avoided, which improves the calibration accuracy. In addition, no duplicated resistor and constant current source is required, which reduces the area occupied by the circuit. Further, the absolute current and the relative current are obtained from the bandgap module and thus have high accuracy. The output signal control module, the constant current source, and the termination resistors of the CML transmitter can be used for transmitting signals after the resistance calibration is finished, which improves the utilization of the circuit module.

    Circuit for generating differential reference voltages, circuit for detecting signal peak, and electronic device

    公开(公告)号:US10855264B1

    公开(公告)日:2020-12-01

    申请号:US16730132

    申请日:2019-12-30

    IPC分类号: H03K5/153 H03K5/1532 H03F3/45

    摘要: A circuit for generating differential reference voltages, a circuit for detecting a signal peak, and an electronic device. In the circuit for generating reference voltages, a common-mode extraction circuit receives a first differential signal and a second differential signal, extracts a common-mode level from the first differential signal and the second differential signal, and applies the common-mode level to a non-inverting input terminal of a first operational amplifier. The first operational amplifier, a main control switch, a first voltage dividing resistor, a second voltage dividing resistor, and a first direct current power source constitute a feedback loop, to generate differential reference voltages matching with the common-mode level. Adjusting a current provided by the first direct current power source can change the differential reference voltages, obtaining a reference for to-be-detected amplitude of the signals. Signal amplitude is detected with high precision, and detection reliability of a peak detecting circuit is improved.

    Switch circuit and high-speed multiplexer-demultiplexer

    公开(公告)号:US10771056B2

    公开(公告)日:2020-09-08

    申请号:US16660136

    申请日:2019-10-22

    IPC分类号: H03K17/62 H03K17/687 H04J3/04

    摘要: A switch circuit and a high-speed multiplexer-demultiplexer are provided. The switch circuit includes an equalization module and an MOS transistor. A gate of the first MOS transistor is connected to an output terminal of the equalization module. An input terminal of the first MOS transistor is connected to a signal source. An output terminal of the first MOS transistor is connected to a subsequent circuit. The equalization module is configured to: supply a turning-on signal to the first MOS transistor in a case that an operation signal is acquired, to turn on the first MOS transistor; and generate a compensation signal for compensating an attenuation of the signal transmitted through the first MOS transistor, and apply the compensation signal to the gate of the first MOS transistor. The switch circuit operates in response to the operation signal.

    Power-on reset circuit
    6.
    发明授权

    公开(公告)号:US10707863B2

    公开(公告)日:2020-07-07

    申请号:US16555080

    申请日:2019-08-29

    IPC分类号: H03K5/153 H03K17/22

    摘要: A power-on reset circuit is provided. During a power-on process of the power-on reset circuit, a threshold voltage of an output signal rstn jumping from a low level to a high level is adjusted by clamp of a voltage at a node c and voltage division between a first resistor and a second resistor, and is controlled to be greater than a threshold voltage of a metal oxide semiconductor device. During a power-off process of the power-on reset circuit, a threshold voltage of the output signal rstn jumping from the high level to the low level is adjusted by increasing a voltage at a node d by means of a third resistor and voltage division between the first resistor and the third resistor, and is controlled to be greater than the threshold voltage of the metal oxide semiconductor device.

    Biphase mark coding transceiver
    7.
    发明授权

    公开(公告)号:US10425101B1

    公开(公告)日:2019-09-24

    申请号:US16049890

    申请日:2018-07-31

    摘要: A Biphase Mark Coding (BMC) transceiver is provided. In the BMC transceiver, an operational amplifier operating in a time division multiplexing manner is used. The operational amplifier is configured as a unity gain buffer, and it is determined whether the BMC transceiver operates as a transmitter or a receiver by selecting different input switches and output switches. In a transmitting mode, a bias current of an input differential pair transistor of the operational amplifier is changed, to change a slew rate, so as to obtain an output waveform with adjustable rising/falling edges of the transmitter.

    Biphase mark coding transmitter
    8.
    发明授权

    公开(公告)号:US10404271B1

    公开(公告)日:2019-09-03

    申请号:US16013447

    申请日:2018-06-20

    IPC分类号: H03M5/12 H03M1/08 H04B1/04

    摘要: A biphase mark coding transmitter is provided. In the biphase mark coding transmitter, a delay control unit performs equal-interval delay processing on data transmitted by a data coding and protocol processing unit. Then, the current-steering digital-to-analog converter is controlled to charge or discharge a resistance-capacitance circuit to obtain an accurately-controlled conversion time. Data with the controlled conversion time is driven to a CC by a unity-gain buffer to generate an output waveform. The technical solution solves the technical problem of a mutual influence between power source systems of a traditional BMC transmitter which is a digital module and a traditional BMC receiver which is an analog module, and the technical problem of a large noise of a power switch and large consumption of chip area and power which are resulted from digital buffers driven by equal-interval data or clocks in a traditional BMC transmitter.