公开(公告)号：US20100217905A1

公开(公告)日：2010-08-26

申请号：US12391373

申请日：2009-02-24

申请人： Lakshminarayana Arimilli ,  Claude Basso ,  Piyush Chaudhary ,  Benard C. Drerup ,  Jody B. Joyner ,  Jan-Bernd Themann ,  Christoph Raisch ,  Colin B. Verrilli

发明人： Lakshminarayana Arimilli ,  Claude Basso ,  Piyush Chaudhary ,  Benard C. Drerup ,  Jody B. Joyner ,  Jan-Bernd Themann ,  Christoph Raisch ,  Colin B. Verrilli

IPC分类号： G06F13/24 ,  G06F9/54

CPC分类号： G06F9/545 ,  G06F9/546

摘要： A synchronization optimized queuing method and device to minimize software/hardware interaction in network interface hardware during an end-of-initiative process, including network adapter queue implementations for network interface hardware for optimized communication in a computer system. An end-of-initiative procedure to ensure that the network interface hardware has received an interrupt enable and to recheck the interrupt queue is unnecessary in the present invention.

摘要翻译： 一种同步优化的排队方法和设备，用于最大程度地减少网络接口硬件中的软件/硬件交互，包括用于计算机系统中优化通信的网络接口硬件的网络适配器队列实现。 在本发明中，确保网络接口硬件已经接收到中断使能并重新检查中断队列的最终主动性过程是不必要的。

公开(公告)号：US08302109B2

公开(公告)日：2012-10-30

申请号：US12391373

申请日：2009-02-24

申请人： Lakshminarayana Arimilli ,  Claude Basso ,  Piyush Chaudhary ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jan-Bernd Themann ,  Christoph Raisch ,  Colin B. Verrilli

发明人： Lakshminarayana Arimilli ,  Claude Basso ,  Piyush Chaudhary ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jan-Bernd Themann ,  Christoph Raisch ,  Colin B. Verrilli

IPC分类号： G06F3/03

CPC分类号： G06F9/545 ,  G06F9/546

摘要： A synchronization optimized queuing method and device to minimize software/hardware interaction in network interface hardware during an end-of-initiative process, including network adapter queue implementations for network interface hardware for optimized communication in a computer system. An end-of-initiative procedure to ensure that the network interface hardware has received an interrupt enable and to recheck the interrupt queue is unnecessary in the present invention.

摘要翻译： 一种同步优化的排队方法和设备，用于最大程度地减少网络接口硬件中的软件/硬件交互，包括用于计算机系统中优化通信的网络接口硬件的网络适配器队列实现。 在本发明中，确保网络接口硬件已经接收到中断使能并重新检查中断队列的最终主动性过程是不必要的。

公开(公告)号：US07715428B2

公开(公告)日：2010-05-11

申请号：US11669419

申请日：2007-01-31

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks, Jr. ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks, Jr. ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC分类号： H04L12/66 ,  H04J3/16 ,  H04J3/22

CPC分类号： H04L47/50

摘要： Mechanisms for processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.

摘要翻译： 提供了用于处理数据处理设备之间的通信的机制。 利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。 此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。 多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。 可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

公开(公告)号：US20080181245A1

公开(公告)日：2008-07-31

申请号：US11669419

申请日：2007-01-31

申请人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

发明人： Claude Basso ,  Jean L. Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Herman D. Dierks ,  Christoph Raisch ,  Jan-Bernd Themann ,  Natarajan Vaidhyanathan ,  Fabrice J. Verplanken ,  Colin B. Verrilli

IPC分类号： H04L12/56

CPC分类号： H04L47/50

摘要： A system and method for multicore processing of communications between data processing devices are provided. With the mechanisms of the illustrative embodiments, a set of techniques that enables sustaining media speed by distributing transmit and receive-side processing over multiple processing cores is provided. In addition, these techniques also enable designing multi-threaded network interface controller (NIC) hardware that efficiently hides the latency of direct memory access (DMA) operations associated with data packet transfers over an input/output (I/O) bus. Multiple processing cores may operate concurrently using separate instances of a communication protocol stack and device drivers to process data packets for transmission with separate hardware implemented send queue managers in a network adapter processing these data packets for transmission. Multiple hardware receive packet processors in the network adapter may be used, along with a flow classification engine, to route received data packets to appropriate receive queues and processing cores for processing.

摘要翻译： 提供了一种用于数据处理设备之间的通信的多核处理的系统和方法。 利用说明性实施例的机制，提供了一组通过在多个处理核上分发发送和接收侧处理来维持媒体速度的技术。 此外，这些技术还可以设计出多线程网络接口控制器（NIC）硬件，可有效地隐藏通过输入/输出（I / O）总线传输数据分组的直接存储器访问（DMA）操作的延迟。 多个处理核心可以使用通信协议栈和设备驱动程序的单独实例同时运行，以处理用于传输的数据分组，其中单独的硬件实现了处理这些数据分组以进行传输的网络适配器中的发送队列管理器。 可以使用网络适配器中的多个硬件接收分组处理器以及流分类引擎将接收到的数据分组路由到适当的接收队列和处理核心进行处理。

公开(公告)号：US08902750B2

公开(公告)日：2014-12-02

申请号：US13150507

申请日：2011-06-01

申请人： Claude Basso ,  Anil Pothireddy ,  Christoph Raisch ,  Saravanan Sethuraman ,  Vibhor K. Srivastava ,  Jan-Bernd Themann ,  Fabrice J. Verplanken

发明人： Claude Basso ,  Anil Pothireddy ,  Christoph Raisch ,  Saravanan Sethuraman ,  Vibhor K. Srivastava ,  Jan-Bernd Themann ,  Fabrice J. Verplanken

IPC分类号： H04L12/801 ,  H04L12/26 ,  H04L29/06 ,  H04L12/823 ,  H04L12/835

CPC分类号： H04L47/10 ,  H04L47/17 ,  H04L47/30 ,  H04L47/32 ,  H04L47/34 ,  H04L69/08

摘要： Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.

摘要翻译： 在由第一网络组件使用的以太网协议和第二网络组件使用的融合增强以太网（CEE）协议之间进行转换，所述第一和第二组件通过CEE转换器耦合，所述CEE转换器通过以下方式耦合：用于从第一网络组件到 第二网络组件：由CEE转换器接收单个CEE协议数据流的业务流定义参数; 由信用管理器计算用于数据流的CEE转换器的出站帧缓冲器中的可用缓冲器空间; 由信用管理器将第一组件的CEE信用驱动程序与计算出的缓冲区空间的大小以及起始序列号和流标识符进行通信; 并由CEE信用驱动程序向CEE转换器响应包括包含流标识符和序列号的专用报头的以太网帧。

公开(公告)号：US20110299394A1

公开(公告)日：2011-12-08

申请号：US13150507

申请日：2011-06-01

申请人： Claude Basso ,  Anil Pothireddy ,  Christoph Raisch ,  Saravanan Sethuraman ,  Vibhor K. Srivastava ,  Jan-Bernd Themann ,  Fabrice J. Verplanken

发明人： Claude Basso ,  Anil Pothireddy ,  Christoph Raisch ,  Saravanan Sethuraman ,  Vibhor K. Srivastava ,  Jan-Bernd Themann ,  Fabrice J. Verplanken

IPC分类号： H04L12/26

CPC分类号： H04L47/10 ,  H04L47/17 ,  H04L47/30 ,  H04L47/32 ,  H04L47/34 ,  H04L69/08

摘要： Translating between an Ethernet protocol used by a first network component and a Converged Enhanced Ethernet (CEE) protocol used by a second network component, the first and second components coupled through a CEE Converter that translates by: for data flow from the first network component to the second network component: receiving, by the CEE converter, traffic flow definition parameters for a single CEE protocol data flow; calculating, by a credit manager, available buffer space in an outbound frame buffer of the CEE converter for the data flow; communicating, by the credit manager to a CEE credit driver of the first component, the calculated size of the buffer space together with a start sequence number and a flow identifier; and responding, by the CEE credit driver to the CEE converter, with Ethernet frames comprising a private header that includes the flow identifier and a sequence number.

摘要翻译： 在由第一网络组件使用的以太网协议和第二网络组件使用的融合增强以太网（CEE）协议之间进行转换，所述第一和第二组件通过CEE转换器耦合，所述CEE转换器通过以下方式耦合：用于从第一网络组件到 第二网络组件：由CEE转换器接收单个CEE协议数据流的业务流定义参数; 由信用管理器计算用于数据流的CEE转换器的出站帧缓冲器中的可用缓冲器空间; 由信用管理器将第一组件的CEE信用驱动程序与计算出的缓冲区空间的大小以及起始序列号和流标识符进行通信; 并由CEE信用驱动程序向CEE转换器响应包括包含流标识符和序列号的专用报头的以太网帧。

公开(公告)号：US08687649B2

公开(公告)日：2014-04-01

申请号：US13042776

申请日：2011-03-08

申请人： William J. Armstrong ,  Claude Basso ,  Chih-Jen Chang ,  Josep Cors ,  Daniel G. Eisenhauer ,  Henry J. May ,  Christoph Raisch ,  Renato J. Recio ,  Colin B. Verrilli ,  Chetan S. Yaliwal

发明人： William J. Armstrong ,  Claude Basso ,  Chih-Jen Chang ,  Josep Cors ,  Daniel G. Eisenhauer ,  Henry J. May ,  Christoph Raisch ,  Renato J. Recio ,  Colin B. Verrilli ,  Chetan S. Yaliwal

IPC分类号： H04J3/22

CPC分类号： H04L69/08 ,  H04L69/324

摘要： A network node that forwards traffic of a converged network received from a source end node receives a second message addressed to the network node, but intended for the source end node. The second message includes at least a portion of a first message originated by the source end node and previously forwarded by the network node. The network node extracts from the first message a source identifier of the source end node in a first communication protocol and determines by reference to a data structure a destination address of the second message in a second communication protocol. The network node modifies the second message to include the destination address and forwards the second message toward the source end node in accordance with the destination address.

摘要翻译： 转发从源端节点接收的融合网络的业务的网络节点接收寻址到网络节点但是用于源端节点的第二消息。 第二消息包括由源端节点发起并且由网络节点先前转发的第一消息的至少一部分。 网络节点从第一消息中提取第一通信协议中的源端节点的源标识符，并且在第二通信协议中通过参考数据结构确定第二消息的目的地地址来确定。 网络节点修改第二个消息以包含目的地址，并根据目的地址向源端节点转发第二个消息。

公开(公告)号：US20120278575A1

公开(公告)日：2012-11-01

申请号：US13547165

申请日：2012-07-12

申请人： Christoph Raisch ,  Jan-Bernd Themann ,  Jonas Eymann ,  Moritz Prinz ,  Enrique Marcial-Simon ,  Thomas Ilsche

发明人： Christoph Raisch ,  Jan-Bernd Themann ,  Jonas Eymann ,  Moritz Prinz ,  Enrique Marcial-Simon ,  Thomas Ilsche

IPC分类号： G06F12/16

CPC分类号： G06F12/02 ,  G06F13/4027

摘要： A method for exchanging message data in a distributed computer system between a sending and a receiving hardware system. The sending hardware system includes a first memory system and a receiving hardware system which includes a second memory system with a second data buffer and a second memory region. The sending hardware system and the receiving hardware system are coupled via a non-transparent bridge unit. The method includes allocating empty memory, writing information about the empty memory, copying payload data directly from the sending hardware system to the empty memory locations, and writing information about the copied payload data to the second data buffer of the second memory system inside the receiving hardware system. A computer program product for carrying out the method is also provided.

摘要翻译： 一种用于在发送和接收硬件系统之间的分布式计算机系统中交换消息数据的方法。 发送硬件系统包括第一存储器系统和接收硬件系统，其包括具有第二数据缓冲器和第二存储器区域的第二存储器系统。 发送硬件系统和接收硬件系统通过不透明的桥接单元耦合。 该方法包括分配空存储器，写入关于空存储器的信息，将有效载荷数据直接从发送硬件系统复制到空存储器单元，以及将关于复制的有效载荷数据的信息写入到接收器内的第二存储器系统的第二数据缓冲器 硬件系统。 还提供了一种用于执行该方法的计算机程序产品。

公开(公告)号：US20110145533A1

公开(公告)日：2011-06-16

申请号：US12966059

申请日：2010-12-13

申请人： Christoph Raisch ,  Jan-Bernd Themann ,  Jonas Eymann ,  Moritz Prinz ,  Enrique Marcial-Simon ,  Thomas Ilsche

发明人： Christoph Raisch ,  Jan-Bernd Themann ,  Jonas Eymann ,  Moritz Prinz ,  Enrique Marcial-Simon ,  Thomas Ilsche

IPC分类号： G06F12/02

CPC分类号： G06F12/02 ,  G06F13/4027

摘要： A method for exchanging message data in a distributed computer system between a sending and a receiving hardware system. The sending hardware system includes a first memory system and a receiving hardware system which includes a second memory system with a second data buffer and a second memory region. The sending hardware system and the receiving hardware system are coupled via a non-transparent bridge unit. The method includes allocating empty memory, writing information about the empty memory, copying payload data directly from the sending hardware system to the empty memory locations, and writing information about the copied payload data to the second data buffer of the second memory system inside the receiving hardware system. A system and computer program product for carrying out the method are also provided.

摘要翻译： 一种用于在发送和接收硬件系统之间的分布式计算机系统中交换消息数据的方法。 发送硬件系统包括第一存储器系统和接收硬件系统，其包括具有第二数据缓冲器和第二存储器区域的第二存储器系统。 发送硬件系统和接收硬件系统通过不透明的桥接单元耦合。 该方法包括分配空存储器，写入关于空存储器的信息，将有效载荷数据直接从发送硬件系统复制到空存储器单元，以及将关于复制的有效载荷数据的信息写入到接收器内的第二存储器系统的第二数据缓冲器 硬件系统。 还提供了一种用于执行该方法的系统和计算机程序产品。

公开(公告)号：US08250260B2

公开(公告)日：2012-08-21

申请号：US12966059

申请日：2010-12-13

申请人： Christoph Raisch ,  Jan-Bernd Themann ,  Jonas Eymann ,  Moritz Prinz ,  Enrique Marcial-Simon ,  Thomas Ilsche

发明人： Christoph Raisch ,  Jan-Bernd Themann ,  Jonas Eymann ,  Moritz Prinz ,  Enrique Marcial-Simon ,  Thomas Ilsche

IPC分类号： G06F3/00

CPC分类号： G06F12/02 ,  G06F13/4027

摘要： A method for exchanging message data in a distributed computer system between a sending and a receiving hardware system. The sending hardware system includes a first memory system and a receiving hardware system which includes a second memory system with a second data buffer and a second memory region. The sending hardware system and the receiving hardware system are coupled via a non-transparent bridge unit. The method includes allocating empty memory, writing information about the empty memory, copying payload data directly from the sending hardware system to the empty memory locations, and writing information about the copied payload data to the second data buffer of the second memory system inside the receiving hardware system. A system and computer program product for carrying out the method are also provided.

摘要翻译： 一种用于在发送和接收硬件系统之间的分布式计算机系统中交换消息数据的方法。 发送硬件系统包括第一存储器系统和接收硬件系统，其包括具有第二数据缓冲器和第二存储器区域的第二存储器系统。 发送硬件系统和接收硬件系统通过不透明的桥接单元耦合。 该方法包括分配空存储器，写入关于空存储器的信息，将有效载荷数据直接从发送硬件系统复制到空存储器单元，以及将关于复制的有效载荷数据的信息写入到接收器内的第二存储器系统的第二数据缓冲器 硬件系统。 还提供了一种用于执行该方法的系统和计算机程序产品。