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    TECHNIQUES FOR CACHE INJECTION IN A PROCESSOR SYSTEM BASED ON A SHARED STATE
    1.
    发明申请
    TECHNIQUES FOR CACHE INJECTION IN A PROCESSOR SYSTEM BASED ON A SHARED STATE 有权
    基于共享状态的处理器系统中缓存注入的技术

    公开(公告)号：US20100262787A1

    公开(公告)日：2010-10-14

    申请号：US12421338

    申请日：2009-04-09

    申请人： Lakshminarayana Baba Arimilli ,  Ravi K. Arimilli ,  Jody B. Joyner ,  William J. Starke

    发明人： Lakshminarayana Baba Arimilli ,  Ravi K. Arimilli ,  Jody B. Joyner ,  William J. Starke

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0815 ,  G06F12/1027 ,  G06F12/123

    摘要： A technique for performing cache injection includes monitoring, at a host fabric interface, snoop responses to an address on a bus. When the snoop responses indicate a data block associated with the address is in a shared state, input/output data associated with the address on the bus is directed to a cache that includes the data block in the shared state and is located physically closer to the host fabric interface than one or more other caches that include the data block associated with the address in the shared state.

    摘要翻译： 用于执行高速缓存注入的技术包括在主机结构接口处监视对总线上的地址的响应。 当窥探响应指示与地址相关联的数据块处于共享状态时，与总线上的地址相关联的输入/输出数据被引导到包括处于共享状态的数据块的高速缓存，并且物理上更靠近 主机结构接口比包括与共享状态中的地址相关联的数据块的一个或多个其他高速缓存。

    Issuing global shared memory operations via direct cache injection to a host fabric interface
    6.
    发明授权
    Issuing global shared memory operations via direct cache injection to a host fabric interface 有权
    通过直接缓存注入向主机结构接口发出全局共享内存操作

    公开(公告)号：US07966454B2

    公开(公告)日：2011-06-21

    申请号：US12024437

    申请日：2008-02-01

    申请人： Lakshimarayana B. Arimilli ,  Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  William J. Starke ,  Hanhong Xue

    发明人： Lakshimarayana B. Arimilli ,  Ravi K. Arimilli ,  Robert S. Blackmore ,  Chulho Kim ,  Ramakrishnan Rajamony ,  William J. Starke ,  Hanhong Xue

    IPC分类号： G06F9/318

    CPC分类号： G06F12/0815 ,  G06F12/0897 ,  G06F12/10

    摘要： A data processing system enables global shared memory (GSM) operations across multiple nodes with a distributed EA-to-RA mapping of physical memory. Each node has a host fabric interface (HFI), which includes HFI windows that are assigned to at most one locally-executing task of a parallel job. The tasks perform parallel job execution, but map only a portion of the effective addresses (EAs) of the global address space to the local, real memory of the task's respective node. The HFI window tags all outgoing GSM operations (of the local task) with the job ID, and embeds the target node and HFI window IDs of the node at which the EA is memory mapped. The HFI window also enables processing of received GSM operations with valid EAs that are homed to the local real memory of the receiving node, while preventing processing of other received operations without a valid EA-to-RA local mapping.

    摘要翻译： 数据处理系统通过物理内存的分布式EA-to-RA映射实现跨多个节点的全局共享存储（GSM）操作。 每个节点都有一个主机结构接口（HFI），它包括分配给并行作业最多一个本地执行任务的HFI窗口。 任务执行并行作业执行，但将全局地址空间的有效地址（EA）的一部分映射到任务相应节点的本地实际存储器。 HFI窗口使用作业ID对所有传出的GSM操作（本地任务）进行标记，并嵌入EA被映射到的节点的目标节点和HFI窗口ID。 HFI窗口还能够利用归属于接收节点的本地实际存储器的有效EA来处理接收的GSM操作，同时防止在没有有效的EA到RA本地映射的情况下处理其他接收到的操作。

    Virtual Barrier Synchronization Cache
    7.
    发明申请
    Virtual Barrier Synchronization Cache 失效
    虚拟障碍同步缓存

    公开(公告)号：US20100257317A1

    公开(公告)日：2010-10-07

    申请号：US12419364

    申请日：2009-04-07

    申请人： Ravi K. Arimilli ,  Guy L. Guthrie ,  Robert A. Cargnoni ,  William J. Starke ,  Derek E. Williams

    发明人： Ravi K. Arimilli ,  Guy L. Guthrie ,  Robert A. Cargnoni ,  William J. Starke ,  Derek E. Williams

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0811 ,  G06F9/522

    摘要： A data processing system includes an interconnect fabric, a system memory coupled to the interconnect fabric and including a virtual barrier synchronization region allocated to storage of virtual barrier synchronization registers (VBSRs), and a plurality of processing units coupled to the interconnect fabric and operable to access the virtual barrier synchronization region of the system memory. Each of the plurality of processing units includes a processor core and a cache memory including a cache array that caches VBSR lines from the virtual barrier synchronization region of the system memory and a cache controller. The cache controller, responsive to a store request from the processor core to update a particular VBSR line, performs a non-blocking update of the cache array in each other of the plurality of processing units contemporaneously holding a copy of the particular VBSR line by transmitting a VBSR update command on the interconnect fabric.

    摘要翻译： 数据处理系统包括互连结构，耦合到互连结构并包括分配给虚拟屏障同步寄存器（VBSR）的存储的虚拟屏障同步区域的系统存储器，以及耦合到互连结构的多个处理单元， 访问系统内存的虚拟屏障同步区域。 多个处理单元中的每一个包括处理器核心和高速缓存存储器，其包括从系统存储器的虚拟屏障同步区域缓存VBSR行的缓存阵列和高速缓存控制器。 高速缓存控制器响应于来自处理器核心的存储请求来更新特定VBSR线路，通过发送来同时保存特定VBSR线路的副本的多个处理单元中的彼此之间的高速缓存阵列的非阻塞更新 互连结构上的VBSR更新命令。

    Method and Apparatus for Handling Multiple Memory Requests Within a Multiprocessor System
    8.
    发明申请
    Method and Apparatus for Handling Multiple Memory Requests Within a Multiprocessor System 有权
    在多处理器系统中处理多个存储器请求的方法和装置

    公开(公告)号：US20090198933A1

    公开(公告)日：2009-08-06

    申请号：US12024181

    申请日：2008-02-01

    申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke

    发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke

    IPC分类号： G06F12/14

    CPC分类号： G06F9/526

    摘要： A method for handling multiple memory requests within a multi-processor system is disclosed. A lock control section is initially assigned to a data block within a system memory. In response to a request for accessing the data block by a processing unit, a determination is made whether or not the lock control section of the data block has been set. If the lock control section has been set, another determination is made whether or not the requesting processing unit is located beyond a predetermined distance from a memory controller. If the requesting processing unit is located beyond a predetermined distance from the memory controller, the requesting processing unit is invited to perform other functions; otherwise, the number of the requesting processing unit is placed in a queue table. However, if the lock control section has not been set, the lock control section of the data block is set, and the access request is allowed.

    摘要翻译： 公开了一种在多处理器系统内处理多个存储器请求的方法。 锁控制部分最初被分配给系统存储器内的数据块。 响应于由处理单元访问数据块的请求，确定数据块的锁定控制部分是否已经被设置。 如果已经设置了锁定控制部分，则另外确定请求处理单元是否位于距离存储器控制器超过预定距离的位置。 如果请求处理单元位于距存储器控制器超过预定距离的位置，则请求处理单元被邀请执行其他功能; 否则，请求处理单元的号码被放置在队列表中。 然而，如果锁定控制部分尚未设置，则数据块的锁定控制部分被设置，并且允许访问请求。

    Behavioral memory mechanism for a data processing system
    9.
    发明授权
    Behavioral memory mechanism for a data processing system 失效
    数据处理系统的行为记忆机制

    公开(公告)号：US06792521B2

    公开(公告)日：2004-09-14

    申请号：US09978364

    申请日：2001-10-16

    申请人： Ravi K. Arimilli ,  William J. Starke

    发明人： Ravi K. Arimilli ,  William J. Starke

    IPC分类号： G06F1202

    CPC分类号： G06F12/1054 ,  G06F12/109

    摘要： A behavioral memory mechanism for a data processing system is disclosed. The data processing system includes a processor, a real memory, a behavioral address generator, and an address translator. The real memory has multiple real address locations, and each of the real address locations is associated with a corresponding one of many virtual address locations. The virtual address locations are divided into two non-overlapping regions, namely, an architecturally visible virtual memory region and a behavioral virtual memory region. The behavioral address generator generates a behavioral virtual memory address associated with the behavioral virtual memory region. The address translator translates the behavioral virtual memory address to a real address associated with the real memory.

    摘要翻译： 公开了一种用于数据处理系统的行为记忆机制。 数据处理系统包括处理器，实际存储器，行为地址生成器和地址转换器。 实际存储器具有多个实际地址位置，并且每个实际地址位置与许多虚拟地址位置中的对应的一个相关联。 虚拟地址位置被分成两个非重叠区域，即，架构上可见的虚拟存储器区域和行为虚拟存储器区域。 行为地址生成器生成与行为虚拟存储器区域相关联的行为虚拟存储器地址。 地址转换器将行为虚拟存储器地址转换为与真实存储器相关联的真实地址。

    Performing a partial cache line storage-modifying operation based upon a hint
    10.
    发明授权
    Performing a partial cache line storage-modifying operation based upon a hint 失效
    基于提示执行部分缓存行存储修改操作

    公开(公告)号：US08332588B2

    公开(公告)日：2012-12-11

    申请号：US13349315

    申请日：2012-01-12

    申请人： Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

    发明人： Ravi K. Arimilli ,  Guy L. Guthrie ,  William J. Starke ,  Derek E. Williams

    IPC分类号： G06F12/04

    CPC分类号： G06F12/0822

    摘要： Analyzing pre-processed code includes identifying at least one storage-modifying construct specifying a storage-modifying memory access to a memory hierarchy of a data processing system and determining if more than one granule of a cache line of data containing multiple granules that is targeted by the storage-modifying construct is subsequently referenced by said pre-processed code. Post-processed code including a storage-modifying instruction corresponding to the at least one storage-modifying construct in the pre-processed code is generated and stored. Generating the post-processed code includes marking the storage-modifying instruction with a partial cache line hint indicating that said storage-modifying instruction targets less than a full cache line of data within a memory hierarchy if the analyzing indicates only one granule of the target cache line will be accessed while the cache line is held in the cache memory and otherwise refraining from marking the storage-modifying instruction with the partial cache line hint.

    摘要翻译： 分析预处理的代码包括识别指定对数据处理系统的存储器层次结构的存储修改存储器访问的至少一个存储修改结构，并且确定是否存在多个颗粒的高速缓存行数据，所述数据包含多个颗粒的高速缓存行是由 存储修改结构随后由所述预处理代码引用。 生成并存储包括与预处理代码中的至少一个存储修改结构对应的存储修改指令的后处理代码。 生成后处理代码包括用部分高速缓存线提示标记存储修改指令，指示所述存储修改指令的目标小于存储器层次结构内的完整高速缓存数据行，如果分析仅指示目标高速缓存的一个颗粒 将高速缓存线保持在高速缓存存储器中，并以其它方式避免使用部分高速缓存线提示来标记存储修改指令。