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    TECHNIQUES FOR CACHE INJECTION IN A PROCESSOR SYSTEM BASED ON A SHARED STATE
    1.
    发明申请
    TECHNIQUES FOR CACHE INJECTION IN A PROCESSOR SYSTEM BASED ON A SHARED STATE 有权
    基于共享状态的处理器系统中缓存注入的技术

    公开(公告)号：US20100262787A1

    公开(公告)日：2010-10-14

    申请号：US12421338

    申请日：2009-04-09

    申请人： Lakshminarayana Baba Arimilli ,  Ravi K. Arimilli ,  Jody B. Joyner ,  William J. Starke

    发明人： Lakshminarayana Baba Arimilli ,  Ravi K. Arimilli ,  Jody B. Joyner ,  William J. Starke

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0815 ,  G06F12/1027 ,  G06F12/123

    摘要： A technique for performing cache injection includes monitoring, at a host fabric interface, snoop responses to an address on a bus. When the snoop responses indicate a data block associated with the address is in a shared state, input/output data associated with the address on the bus is directed to a cache that includes the data block in the shared state and is located physically closer to the host fabric interface than one or more other caches that include the data block associated with the address in the shared state.

    摘要翻译： 用于执行高速缓存注入的技术包括在主机结构接口处监视对总线上的地址的响应。 当窥探响应指示与地址相关联的数据块处于共享状态时，与总线上的地址相关联的输入/输出数据被引导到包括处于共享状态的数据块的高速缓存，并且物理上更靠近 主机结构接口比包括与共享状态中的地址相关联的数据块的一个或多个其他高速缓存。

    Cluster-wide system clock in a multi-tiered full-graph interconnect architecture
    8.
    发明授权
    Cluster-wide system clock in a multi-tiered full-graph interconnect architecture 有权
    多层全图互连架构中的群集范围的系统时钟

    公开(公告)号：US07921316B2

    公开(公告)日：2011-04-05

    申请号：US11853522

    申请日：2007-09-11

    申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

    发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

    IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/12

    CPC分类号： G06F1/10 ,  G06F1/12

    摘要： Mechanisms for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

    摘要翻译： 提供了一种在多层全图（MTFG）互连架构中提供集群范围的系统时钟的机制。 计算群集中的每个处理器芯片发送的心跳信号同步。 基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。 结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。 提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。

    System and Method for Performing Dynamic Request Routing Based on Broadcast Source Request Information
    9.
    发明申请
    System and Method for Performing Dynamic Request Routing Based on Broadcast Source Request Information 有权
    基于广播源请求信息执行动态请求路由的系统和方法

    公开(公告)号：US20090198958A1

    公开(公告)日：2009-08-06

    申请号：US12024553

    申请日：2008-02-01

    申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

    发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

    IPC分类号： G06F13/14 ,  G06F9/02

    CPC分类号： H04L45/122 ,  H04L45/06

    摘要： A system and method for performing dynamic request routing based on broadcast source request information are provided. Each processor chip in the system may use a synchronized heartbeat signal it generates to provide source request information to each of the other processor chips in the system. The source request information identifies the number of active source requests sent by the processor chip that originated the heartbeat signal. The source request information from each of the processor chips in the system may be used by the processor chips in determining optimal routing paths for data from a source processor chip to a destination processor chip. As a result, the congestion of data for processing at each of the processor chips along each possible routing path may be taken into account when selecting to which processor chip to forward data.

    摘要翻译： 提供了一种基于广播源请求信息进行动态请求路由的系统和方法。 系统中的每个处理器芯片可以使用其产生的同步心跳信号来向系统中的每个其他处理器芯片提供源请求信息。 源请求信息标识由发起心跳信号的处理器芯片发送的活动源请求的数量。 来自系统中的每个处理器芯片的源请求信息可被处理器芯片用于确定用于从源处理器芯片到目的地处理器芯片的数据的最佳路由路径。 结果，当选择哪个处理器芯片来转发数据时，可以考虑在每个可能的路由路径处的每个处理器芯片处理数据的拥塞。

    System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture
    10.
    发明授权
    System for providing a cluster-wide system clock in a multi-tiered full-graph interconnect architecture 有权
    用于在多层全图互连架构中提供集群范围的系统时钟的系统

    公开(公告)号：US07827428B2

    公开(公告)日：2010-11-02

    申请号：US11848440

    申请日：2007-08-31

    申请人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

    发明人： Lakshminarayana B. Arimilli ,  Ravi K. Arimilli ,  Bernard C. Drerup ,  Jody B. Joyner ,  Jerry D. Lewis

    IPC分类号： G06F1/00 ,  G06F1/04 ,  G06F1/12

    CPC分类号： G06F1/12 ,  H04J3/0685 ,  H04Q2213/13092 ,  H04Q2213/13214 ,  H04Q2213/13322 ,  H04Q2213/1336

    摘要： A system for providing a cluster-wide system clock in a multi-tiered full graph (MTFG) interconnect architecture are provided. Heartbeat signals transmitted by each of the processor chips in the computing cluster are synchronized. Internal system clock signals are generated in each of the processor chips based on the synchronized heartbeat signals. As a result, the internal system clock signals of each of the processor chips are synchronized since the heartbeat signals, that are the basis for the internal system clock signals, are synchronized. Mechanisms are provided for performing such synchronization using direct couplings of processor chips within the same processor book, different processor books in the same supernode, and different processor books in different supernodes of the MTFG interconnect architecture.

    摘要翻译： 提供了一种用于在多层全图（MTFG）互连架构中提供集群范围的系统时钟的系统。 计算群集中的每个处理器芯片发送的心跳信号同步。 基于同步的心跳信号，在每个处理器芯片中产生内部系统时钟信号。 结果，每个处理器芯片的内部系统时钟信号被同步，因为作为内部系统时钟信号的基础的心跳信号被同步。 提供了用于使用同一处理器书中的处理器芯片的直接耦合，同一超级节点中的不同处理器书以及MTFG互连体系结构的不同超节点中的不同处理器簿来执行这种同步的机制。