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公开(公告)号:US20080155280A1
公开(公告)日:2008-06-26
申请号:US11615749
申请日:2006-12-22
申请人: Lance Hacking , Belliappa Kuttana , Rajesh Patel , Ashish Choubal , Terry Fletcher , Steven S. Varnum , Binta Patel
发明人: Lance Hacking , Belliappa Kuttana , Rajesh Patel , Ashish Choubal , Terry Fletcher , Steven S. Varnum , Binta Patel
IPC分类号: G06F1/00
CPC分类号: G06F1/3203 , G06F1/3253 , Y02D10/151
摘要: A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.
摘要翻译: 使用外部电路减少集成电路的I / O引脚中的空闲漏电功率的方法。 最初,封装上的I / O引脚被细分为那些也将保持上电状态的引脚,以及在空闲状态下断电的引脚。 当系统进入低功耗模式时,信号被发送到外部电路。 该信号通知I / O引脚始终保持通电状态,以通知外部电路关闭另一组I / O引脚。
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公开(公告)号:US08392728B2
公开(公告)日:2013-03-05
申请号:US11615749
申请日:2006-12-22
申请人: Lance Hacking , Belliappa Kuttanna , Rajesh Patel , Ashish Choubal , Terry Fletcher , Steven S. Varnum , Binta Patel
发明人: Lance Hacking , Belliappa Kuttanna , Rajesh Patel , Ashish Choubal , Terry Fletcher , Steven S. Varnum , Binta Patel
CPC分类号: G06F1/3203 , G06F1/3253 , Y02D10/151
摘要: A method to reduce idle leakage power in I/O pins of an integrated circuit using external circuitry. Initially, I/O pins on a package are subdivided into those that will also remain powered up and those that will power down during idle state. When a system enters a low power mode, a signal is sent to the external circuitry. The signal notifies the I/O pins that always remain powered up to notify the external circuitry to power down the other set of I/O pins.
摘要翻译: 使用外部电路减少集成电路的I / O引脚中的空闲漏电功率的方法。 最初,封装上的I / O引脚被细分为那些也将保持上电状态的引脚,以及在空闲状态下断电的引脚。 当系统进入低功耗模式时,信号被发送到外部电路。 该信号通知I / O引脚始终保持通电状态,以通知外部电路关闭另一组I / O引脚。
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