公开(公告)号：US4947393A

公开(公告)日：1990-08-07

申请号：US242565

申请日：1988-09-12

申请人： Richard F. Paul ,  Larry L. Byers ,  Wayne A. Michaelson

发明人： Richard F. Paul ,  Larry L. Byers ,  Wayne A. Michaelson

IPC分类号： G06F12/16 ,  G06F11/00 ,  G06F11/30 ,  H01R9/03 ,  H01R24/00

CPC分类号： G06F11/0757

摘要： The logic cards for a main storage unit or computer logic which receive request operations for access to portions of the memory or logic are divided into banks or elements. When a request operation attempts to access one of the elements a return busy signal is raised from that element. The present invention structure generates a predicted busy signal which occurs during the same time the return busy signal should be activated or operable. The return busy signal and predict busy signal are compared in novel circuitry to verify that the element performing the operaton is in fact performing an operation during the predetermined time slot allowed for performance of the requested operation. Fault signals for bank invalidation are stored in internal check trap circuitry for future reference when the requestor raises a subsequent request operation.

摘要翻译： 用于接收存储器或逻辑的部分的请求操作的主存储单元或计算机逻辑的逻辑卡被划分为存储体或元件。 当请求操作尝试访问元素之一时，从该元素引起返回忙信号。 本发明的结构产生一个预测的忙信号，该预测的忙信号在同一时间内应该被激活或可操作的。 在新电路中比较返回忙信号和预测忙信号，以验证执行操作的元件实际上是在允许执行所请求的操作的预定时隙期间执行操作。 银行无效的故障信号存储在内部检查陷阱电路中，以供将来参考，当请求者提出后续请求操作时。

公开(公告)号：US4933908A

公开(公告)日：1990-06-12

申请号：US264113

申请日：1988-10-28

申请人： Larry L. Byers ,  Wayne A. Michaelson ,  Richard F. Paul

发明人： Larry L. Byers ,  Wayne A. Michaelson ,  Richard F. Paul

IPC分类号： G11C11/406 ,  G11C29/02

CPC分类号： G11C29/02 ,  G11C11/406

摘要： A dynamic random access memory (DRAM) memory refreshing scheme utilizes at least two separate refresh channels. Each of the channels consists of a pair of identical counters which are coupled through two different types of timing chains. One of the timing chains is associated with one of the counters and generates a refresh request signal, while the other timing channel generates a refresh error signal. As long as the refresh error signal matches the refresh request signal, no error is present, and a validated refresh request signal will be generated from that timing channel and supplied to an OR gate to refresh all of the memory banks for the memory. Whenever a mismatch occurs between the refresh error signal and the refresh request for one of the refresh channels, the validated refresh request signal for that channel will be inoperable, and continued refreshing operation of the memory depends on the supply of the validated refresh request signals through the other channel in which the refresh request signal and the refresh error signals still match.

摘要翻译： 动态随机存取存储器（DRAM）存储器刷新方案利用至少两个单独的刷新通道。 每个通道由一对相同的计数器组成，它们通过两种不同类型的定时链耦合。 定时链中的一个与计数器之一相关联，并产生刷新请求信号，而另一个定时通道产生刷新误差信号。 只要刷新误差信号与刷新请求信号一致，则不存在错误，并且将从该定时信道生成经过验证的刷新请求信号，并提供给或门以刷新存储器的所有存储体。 每当刷新误差信号与刷新信道之一的刷新请求之间发生不匹配时，该信道的经验证的刷新请求信号将是不可操作的，并且存储器的继续刷新操作取决于经过验证的刷新请求信号的供应 刷新请求信号和刷新错误信号仍然匹配的另一个通道。

公开(公告)号：US07015740B1

公开(公告)日：2006-03-21

申请号：US10281503

申请日：2002-10-28

申请人： Eugene M. Feinberg ,  Richard F. Paul ,  Philip R. Manela

发明人： Eugene M. Feinberg ,  Richard F. Paul ,  Philip R. Manela

IPC分类号： H03H11/26

CPC分类号： G11C29/028 ,  G01R31/31725 ,  G06F1/04 ,  G11C29/02 ,  G11C29/50012 ,  H03L7/0805 ,  H03L7/0812 ,  H03L7/0997

摘要： A circuit including a sensing circuit, which includes a first delay circuit and a tuning circuit. The tuning circuit includes a sense counter and a reference counter. The sense counter is coupled to the first delay circuit and is configured to count a number of oscillations provided by the first delay circuit and provide a notification to the tuning circuit when the sense counter reaches a threshold value. The reference counter is coupled to the sense counter and a reference clock. The reference counter is configured to store a reference time which represents a time elapsed for the sense counter to reach the threshold value. Also included in the circuit is a second delay circuit coupled to the sensing circuit.

摘要翻译： 一种包括感测电路的电路，其包括第一延迟电路和调谐电路。 调谐电路包括感测计数器和参考计数器。 感测计数器耦合到第一延迟电路，并且被配置为对由第一延迟电路提供的振荡数进行计数，并且当感测计数器达到阈值时向调谐电路提供通知。 参考计数器耦合到感测计数器和参考时钟。 参考计数器被配置为存储参考时间，其表示感测计数器经过的时间达到阈值。 电路中还包括耦合到感测电路的第二延迟电路。

公开(公告)号：US5696693A

公开(公告)日：1997-12-09

申请号：US414881

申请日：1995-03-31

申请人： Mark D. Aubel ,  Arthur F. Boehm ,  Joseph P. Kerzman ,  James E. Rezek ,  John T. Rusterholz ,  Richard F. Paul

发明人： Mark D. Aubel ,  Arthur F. Boehm ,  Joseph P. Kerzman ,  James E. Rezek ,  John T. Rusterholz ,  Richard F. Paul

IPC分类号： G06F17/50

CPC分类号： G06F17/5072

摘要： A method used by a computer-aided design system for placing logic functions and cells in a floor plan of a very large scale integrated circuit chip. The structure of a set of selected logic functions and cells to be placed is compared to a set of selected logic functions and cells which have previously been placed in the floor plan. If the number of cells and the structure of the sets are analogous, the selected logic functions and cells to be placed are automatically assigned physical positions in the floor plan based on the physical position and structure of the selected logic functions and cells that have already been placed, and on an orientation mode. The orientation mode provides for the reflection of the placement of the selected logic functions and cells about the horizontal axis, the vertical axis, or both the horizontal and vertical axes. The size of the sets of selected logic functions and cells may be arbitrarily large, thereby providing advantages over simple manual placement of logic functions and cells in a floor plan.

摘要翻译： 计算机辅助设计系统用于将逻辑功能和单元放置在大规模集成电路芯片的平面图中的方法。 一组选定的逻辑功能和要放置的单元的结构与先前已经放置在平面图中的一组选定的逻辑功能和单元进行比较。 如果单元的数量和组的结构是类似的，则所选择的逻辑功能和要放置的单元基于所选择的逻辑功能和已经被存储的单元的物理位置和结构自动地在平面图中分配物理位置 放置，并在定向模式。 取向模式提供了所选逻辑功能和单元格围绕水平轴，垂直轴或水平轴和垂直轴的位置的反射。 所选择的逻辑功能和单元组的大小可以是任意大的，从而提供了优于在平面图中简单地手动放置逻辑功能和单元的优点。

公开(公告)号：US5819072A

公开(公告)日：1998-10-06

申请号：US671432

申请日：1996-06-27

申请人： Louis B. Bushard ,  Peter B. Criswell ,  Douglas A. Fuller ,  James E. Rezek ,  Richard F. Paul

发明人： Louis B. Bushard ,  Peter B. Criswell ,  Douglas A. Fuller ,  James E. Rezek ,  Richard F. Paul

IPC分类号： G06F17/50 ,  G06F9/455

CPC分类号： G06F17/5031

摘要： Method for performing critical path timing analysis on a circuit design having different timing constraints for multiple parallel paths. Method includes clearing the state of the circuit design, setting control lines in the circuit design to a selected set of control signals, and identifying blocking nets of the circuit design to be flagged for timing analysis by simulating the circuit design with the selected set of control signals as input signals. Identified blocking points are added to a list which identifies paths in the circuit design to be analyzed. All possible sets of control signals are processed. Timing analysis is then performed on the circuit design using the list as input data. A critical step is the identification of the blocking points. Blocking points are identified for each net input to a gate in the circuit design having an unknown value, and a known value on an output net from the gate for the selected set of control signals. Blocking points input to the timing analysis tool ensure that these nets are analyzed during critical path timing analysis, so all possible timing violations in the circuit design are detected.

摘要翻译： 对于对于多个并行路径具有不同时序约束的电路设计执行关键路径时序分析的方法。 方法包括清除电路设计的状态，将电路设计中的控制线设置为所选择的一组控制信号，以及通过使用所选择的一组控制来模拟电路设计来识别要标记的时序分析的电路设计的阻塞网 信号作为输入信号。 识别的阻塞点被添加到标识要分析的电路设计中的路径的列表。 处理所有可能的控制信号组。 然后使用列表作为输入数据对电路设计进行时序分析。 关键的一步是识别阻塞点。 针对具有未知值的电路设计中的栅极的每个净输入识别阻塞点，以及针对所选择的一组控制信号的来自栅极的输出网上的已知值。 输入到定时分析工具的阻塞点确保在关键路径时序分析期间对这些网络进行分析，因此检测到电路设计中的所有可能的定时违规。