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公开(公告)号：US4947393A
公开(公告)日：1990-08-07
申请号：US242565
申请日：1988-09-12
CPC分类号： G06F11/0757
摘要： The logic cards for a main storage unit or computer logic which receive request operations for access to portions of the memory or logic are divided into banks or elements. When a request operation attempts to access one of the elements a return busy signal is raised from that element. The present invention structure generates a predicted busy signal which occurs during the same time the return busy signal should be activated or operable. The return busy signal and predict busy signal are compared in novel circuitry to verify that the element performing the operaton is in fact performing an operation during the predetermined time slot allowed for performance of the requested operation. Fault signals for bank invalidation are stored in internal check trap circuitry for future reference when the requestor raises a subsequent request operation.
摘要翻译： 用于接收存储器或逻辑的部分的请求操作的主存储单元或计算机逻辑的逻辑卡被划分为存储体或元件。 当请求操作尝试访问元素之一时，从该元素引起返回忙信号。 本发明的结构产生一个预测的忙信号，该预测的忙信号在同一时间内应该被激活或可操作的。 在新电路中比较返回忙信号和预测忙信号，以验证执行操作的元件实际上是在允许执行所请求的操作的预定时隙期间执行操作。 银行无效的故障信号存储在内部检查陷阱电路中，以供将来参考，当请求者提出后续请求操作时。
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公开(公告)号：US4933908A
公开(公告)日：1990-06-12
申请号：US264113
申请日：1988-10-28
IPC分类号： G11C11/406 , G11C29/02
CPC分类号： G11C29/02 , G11C11/406
摘要： A dynamic random access memory (DRAM) memory refreshing scheme utilizes at least two separate refresh channels. Each of the channels consists of a pair of identical counters which are coupled through two different types of timing chains. One of the timing chains is associated with one of the counters and generates a refresh request signal, while the other timing channel generates a refresh error signal. As long as the refresh error signal matches the refresh request signal, no error is present, and a validated refresh request signal will be generated from that timing channel and supplied to an OR gate to refresh all of the memory banks for the memory. Whenever a mismatch occurs between the refresh error signal and the refresh request for one of the refresh channels, the validated refresh request signal for that channel will be inoperable, and continued refreshing operation of the memory depends on the supply of the validated refresh request signals through the other channel in which the refresh request signal and the refresh error signals still match.
摘要翻译： 动态随机存取存储器（DRAM）存储器刷新方案利用至少两个单独的刷新通道。 每个通道由一对相同的计数器组成，它们通过两种不同类型的定时链耦合。 定时链中的一个与计数器之一相关联，并产生刷新请求信号，而另一个定时通道产生刷新误差信号。 只要刷新误差信号与刷新请求信号一致，则不存在错误，并且将从该定时信道生成经过验证的刷新请求信号，并提供给或门以刷新存储器的所有存储体。 每当刷新误差信号与刷新信道之一的刷新请求之间发生不匹配时，该信道的经验证的刷新请求信号将是不可操作的，并且存储器的继续刷新操作取决于经过验证的刷新请求信号的供应 刷新请求信号和刷新错误信号仍然匹配的另一个通道。
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3.发明授权
公开(公告)号：US5539888A
公开(公告)日：1996-07-23
申请号：US369862
申请日：1995-01-06
CPC分类号： G06F9/30058 , G06F9/3877
摘要： A method and apparatus for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby a branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation.
摘要翻译： 一种用于通过包含可编程微处理器和由双向总线连接的多个VLSI门阵列的数据处理系统来执行条件转移指令的方法和装置，由此从驻留在执行异步的VLSI门阵列上的存储位置获得分支条件， 微处理器外部。 分支条件与分支目标地址的获取和程序计数器的递增并行获取和评估。 微处理器根据分支条件评估的结果改变指令序列控制。
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4.发明授权
公开(公告)号：US5488702A
公开(公告)日：1996-01-30
申请号：US233199
申请日：1994-04-26
CPC分类号： G06F11/1004
摘要： A system and method for detecting errors during the storage and retrieval of file information between a file cache system and a host computer system utilizes a block check sequence key as redundant data included in each block of file data transferred. The block check sequence key is generated by key generation logic and accompanies each block of file data stored in the file cache system by the host computer system. The block check sequence key is a compressed representation of the data within the selected block, as well as unique file and block identification information supplied by the requester of the write operation. When the block is retrieved from the file cache system, the system generates a new block check sequence key based on the data within the retrieved block and the unique file and block identification information supplied by the requester of the read operation. Validation logic ensures that if the retrieved key and the newly generated key does not match, an error signal is activated.
摘要翻译： 用于在文件高速缓存系统和主机系统之间的文件信息的存储和检索期间检测错误的系统和方法利用块校验序列密钥作为包含在传送的每个文件数据块中的冗余数据。 块检查序列密钥由密钥生成逻辑生成，并且由主计算机系统伴随存储在文件高速缓存系统中的每个文件数据块。 块检查序列密钥是所选块内的数据的压缩表示，以及由写操作的请求者提供的唯一的文件和块标识信息。 当从文件缓存系统检索到该块时，系统基于检索到的块内的数据和由读取操作的请求者提供的唯一文件和块识别信息生成新的块校验序列密钥。 验证逻辑确保如果检索到的密钥和新生成的密钥不匹配，则会激活错误信号。
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公开(公告)号：US5032984A
公开(公告)日：1991-07-16
申请号：US246509
申请日：1988-09-19
IPC分类号： G06F13/16
CPC分类号： G06F13/1647
摘要： A system for apportioning serially supplied data among eight contending memory banks tends to equalize usage among the banks despite their arrangement in a predetermined, sequential priority. Each bank has a data hold register, an OR logic gate to generate a request signal whenever its register contains data, and a negative AND gate for enabling the bank for clearing data from its register. All except the lowest priority bank further include a blocking latch and an enabling NOR gate. Each blocking latch is set when its associated bank is enabled, and then inhibits its associated AND gate and each higher priority AND gate, while enabling each lower priority NOR gate. Each enabled NOR gate provides an enabling signal to all lower priority AND gates. When the lowest priority AND gate is enabled by the NOR gates and its request signal, all blocking latches are cleared. The banks thus are utilized in a sequence that is maintained even if one or more banks are bypassed on occasion.
摘要翻译： 在八个竞争存储器组中用于分配串行提供的数据的系统倾向于使得各个存储体之间的使用相等，尽管它们以预定的顺序优先级排列。 每个存储体都有一个数据保持寄存器，一个OR逻辑门，每当其寄存器包含数据时产生请求信号，以及一个用于使该存储体从其寄存器中清除数据的负与门。 所有除最低优先级组之外的所有其他进一步包括阻塞锁存器和使能NOR门。 当其相关联的组使能时，每个阻塞锁存器被置1，然后禁止其相关联的与门和每个较高优先级的与门，同时使能每个较低优先级的或非门。 每个使能的或非门向所有较低优先级的与门提供使能信号。 当通过或非门及其请求信号使能最低优先级AND门时，所有阻塞锁存器被清零。 因此，即使有时候绕过一个或多个银行，银行也被维持在一个序列中。
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公开(公告)号：US5535405A
公开(公告)日：1996-07-09
申请号：US172657
申请日：1993-12-23
CPC分类号： G06F11/1637 , G06F11/1625 , G06F9/30036 , G06F9/3885
摘要： A microsequencer bus controller system provides a flexible and efficient mechanism for controlling multiple gate arrays called stations embedded within a larger computer system. A control store memory, loaded at system initialization time, holds fixed-length instructions simultaneously executed by dual reduced instruction set (RISC) microprocessors which interface with the multiple stations over a bi-directional bus. The master microprocessor compares the result of the processing of each instruction with the slave microprocessor's result to detect any differences, thereby minimizing error latency. Master and slave microprocessors each control half of the stations on the bus. Data widths of 32-bit and 36-bit words are supported by the microprocessors, bus, and stations.
摘要翻译： 微定序器总线控制器系统提供了一种灵活和有效的机制，用于控制被称为站内嵌入较大计算机系统的多个门阵列。 在系统初始化时刻加载的控制存储器存储由双精简指令集（RISC）微处理器同时执行的固定长度指令，它们通过双向总线与多个站进行接口。 主微处理器将每个指令的处理结果与从属微处理器的结果进行比较，以检测任何差异，从而最大限度地减少错误延迟。 主从微处理器控制总线上的一半站。 32位和36位字的数据宽度由微处理器，总线和站支持。
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7.发明授权System for processing shift, mask, and merge operations in one instruction 失效用于在一个指令中处理移位，掩码和合并操作的系统
公开(公告)号：US5487159A
公开(公告)日：1996-01-23
申请号：US172526
申请日：1993-12-23
CPC分类号： G06F9/30029 , G06F9/30032
摘要： A method and system for executing shift, mask, and merge operations on two operands specified by one instruction contains two registers holding operand data and separate shift, mask, and merge logic. A programmer-defined set of mask and merge indicators controls the mask and merge operations. Each mask and merge indicator is represented as a single bit but controls a pair of bits in an operand. If the first operand is selected by the programmer, it is shifted and then masked. The result of the shift and mask operations is merged with the second operand. If the second operand is selected, it is shifted and masked, and the result is merged with the first operand. Final results are stored for processing by subsequent instructions.
摘要翻译： 用于对由一个指令指定的两个操作数执行移位，掩码和合并操作的方法和系统包含保存操作数数据和分离的移位，掩码和合并逻辑的两个寄存器。 由程序员定义的掩码和合并指示符集合可以控制掩码和合并操作。 每个掩码和合并指示符都表示为单个位，但控制操作数中的一对位。 如果程序员选择了第一个操作数，则它被移位然后被屏蔽。 移位和掩码操作的结果与第二个操作数合并。 如果选择了第二个操作数，则它被移位和屏蔽，结果与第一个操作数合并。 存储最终结果以供后续指令处理。
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公开(公告)号：US5257382A
公开(公告)日：1993-10-26
申请号：US667790
申请日：1991-03-11
CPC分类号： G06F13/1647
摘要： A system for apportioning serially supplied data among eight contending memory banks tends to equalize usage among the banks despite their arrangement in a predetermined, sequential priority. Each bank has a data hold register, an OR logic gate to generate a request signal whenever its register contains data, and a negative AND gate for enabling the bank for clearing data from its register. All except the lowest priority bank further include a blocking latch and an enabling NOR gate. Each blocking latch is set when its associated bank is enabled, and then inhibits its associated AND gate and each higher priority AND gate, while enabling each lower priority NOR gate. Each enabled NOR gate provides an enabling signal to all lower priority AND gates. When the lowest priority AND gate is enabled by the NOR gates and its request signal, all blocking latches are cleared. The banks thus are utilized in a sequence that is maintained even if one or more banks are bypassed on occasion.
摘要翻译： 在八个竞争存储器组中用于分配串行提供的数据的系统倾向于使得各个存储体之间的使用相等，尽管它们以预定的顺序优先级排列。 每个存储体都有一个数据保持寄存器，一个OR逻辑门，每当其寄存器包含数据时产生请求信号，以及一个用于使该存储体从其寄存器中清除数据的负与门。 所有除最低优先级组之外的所有其他进一步包括阻塞锁存器和使能NOR门。 当其相关联的组使能时，每个阻塞锁存器被置1，然后禁止其相关联的与门和每个较高优先级的与门，同时使能每个较低优先级的或非门。 每个使能的或非门向所有较低优先级的与门提供使能信号。 当通过或非门及其请求信号使能最低优先级AND门时，所有阻塞锁存器被清零。 因此，即使有时候绕过一个或多个银行，银行也被维持在一个序列中。
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9.发明授权System and method for executing branch instructions wherein branch target addresses are dynamically selectable under programmer control from writable branch address tables 失效用于执行分支指令的系统和方法，其中分支目标地址在可编程分支地址表的编程器控制下可动态地选择
公开(公告)号：US5471597A
公开(公告)日：1995-11-28
申请号：US352299
申请日：1994-12-08
CPC分类号： G06F9/30058 , G06F9/262
摘要： A system and method for executing conditional branch instructions by a processor using dynamic branch address tables containing branch target addresses. The branch target addresses are selected by the result of a computation of fields in the branch instruction and an index generated during the execution of previous instructions. The relevant fields include the base address of a branch address table and a mask value. The contents, size, and location of the branch address tables in a random-access-memory local store may be changed during run-time by program control.
摘要翻译： 一种用于使用包含分支目标地址的动态分支地址表由处理器执行条件分支指令的系统和方法。 通过分支指令中的字段的计算结果和在执行先前指令期间生成的索引来选择分支目标地址。 相关字段包括分支地址表的基址和掩码值。 随机访问存储器本地存储器中的分支地址表的内容，大小和位置可以在运行时通过程序控制来改变。
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公开(公告)号：US5423030A
公开(公告)日：1995-06-06
申请号：US120093
申请日：1993-09-13
CPC分类号： G06F11/0745 , G06F11/0751 , G06F11/0793
摘要： A bus control and error detection system is provided for a bus system in which data and address signals are transferred between a microsequencer and a number of operational stations which are coupled to the bus. Tri-state drivers are employed in the microsequencer and in the stations which are constructed such that two of the three states of these tri-state drivers are utilized to provide the two states of binary logic operation, and the third state is a high impedance state that protects the components that are coupled to the bus during predefined abort condition which are detected in the system. An abort detection circuit is included in each of the operational stations which is coupled to receive control signals from the microsequencer and which is constructed to emit an ABORT signal output to the microsequencer when the control signals indicate that an abort condition has occurred for the associated operational station. The ABORT signal causes the tri-state driver in the microsequencer to switch to its high impedance state and the microsequencer and transmit LOCK BUS signals to all of the operational stations in order to switch their tri-state drivers to their high impedance states.
摘要翻译： 为总线系统提供总线控制和错误检测系统，其中数据和地址信号在微定序器和耦合到总线的多个操作站之间传送。 三态驱动器被采用在微定序器中和在这些被构造为使得三态驱动器的三种状态中的两个被用于提供二态逻辑运算的两种状态的站中，并且第三状态是高阻抗状态 其在系统中检测到的预定中止条件期间保护耦合到总线的组件。 在每个操作站中包括中止检测电路，其被耦合以从微定序器接收控制信号，并且当控制信号指示已经针对相关联的操作发生了中止条件时被构造为发射输出到微定序器的ABORT信号 站。 ABORT信号使微定序器中的三态驱动器切换到其高阻抗状态，并将微锁定器发送LOCK BUS信号到所有操作站，以便将它们的三态驱动器切换到高阻状态。
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