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公开(公告)号：US4947393A
公开(公告)日：1990-08-07
申请号：US242565
申请日：1988-09-12
CPC分类号： G06F11/0757
摘要： The logic cards for a main storage unit or computer logic which receive request operations for access to portions of the memory or logic are divided into banks or elements. When a request operation attempts to access one of the elements a return busy signal is raised from that element. The present invention structure generates a predicted busy signal which occurs during the same time the return busy signal should be activated or operable. The return busy signal and predict busy signal are compared in novel circuitry to verify that the element performing the operaton is in fact performing an operation during the predetermined time slot allowed for performance of the requested operation. Fault signals for bank invalidation are stored in internal check trap circuitry for future reference when the requestor raises a subsequent request operation.
摘要翻译： 用于接收存储器或逻辑的部分的请求操作的主存储单元或计算机逻辑的逻辑卡被划分为存储体或元件。 当请求操作尝试访问元素之一时，从该元素引起返回忙信号。 本发明的结构产生一个预测的忙信号，该预测的忙信号在同一时间内应该被激活或可操作的。 在新电路中比较返回忙信号和预测忙信号，以验证执行操作的元件实际上是在允许执行所请求的操作的预定时隙期间执行操作。 银行无效的故障信号存储在内部检查陷阱电路中，以供将来参考，当请求者提出后续请求操作时。
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公开(公告)号：US4933908A
公开(公告)日：1990-06-12
申请号：US264113
申请日：1988-10-28
IPC分类号： G11C11/406 , G11C29/02
CPC分类号： G11C29/02 , G11C11/406
摘要： A dynamic random access memory (DRAM) memory refreshing scheme utilizes at least two separate refresh channels. Each of the channels consists of a pair of identical counters which are coupled through two different types of timing chains. One of the timing chains is associated with one of the counters and generates a refresh request signal, while the other timing channel generates a refresh error signal. As long as the refresh error signal matches the refresh request signal, no error is present, and a validated refresh request signal will be generated from that timing channel and supplied to an OR gate to refresh all of the memory banks for the memory. Whenever a mismatch occurs between the refresh error signal and the refresh request for one of the refresh channels, the validated refresh request signal for that channel will be inoperable, and continued refreshing operation of the memory depends on the supply of the validated refresh request signals through the other channel in which the refresh request signal and the refresh error signals still match.
摘要翻译： 动态随机存取存储器（DRAM）存储器刷新方案利用至少两个单独的刷新通道。 每个通道由一对相同的计数器组成，它们通过两种不同类型的定时链耦合。 定时链中的一个与计数器之一相关联，并产生刷新请求信号，而另一个定时通道产生刷新误差信号。 只要刷新误差信号与刷新请求信号一致，则不存在错误，并且将从该定时信道生成经过验证的刷新请求信号，并提供给或门以刷新存储器的所有存储体。 每当刷新误差信号与刷新信道之一的刷新请求之间发生不匹配时，该信道的经验证的刷新请求信号将是不可操作的，并且存储器的继续刷新操作取决于经过验证的刷新请求信号的供应 刷新请求信号和刷新错误信号仍然匹配的另一个通道。
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3.发明授权Processor communications bus having address lines selecting different storage locations based on selected control lines 失效处理器通信总线，其具有基于所选择的控制线选择不同存储位置的地址线
公开(公告)号：US5519876A
公开(公告)日：1996-05-21
申请号：US172629
申请日：1993-12-23
CPC分类号： G06F12/063
摘要： A bus architecture includes address lines, data lines, and control signals to allow a processor to communicate with a VLSI gate array. The address lines are interpreted by the VLSI gate array to select either multi-bit registers or single bit designators resident on the VLSI gate array depending on which control signal is received from the processor. Dual address decode logic on the VLSI gate array senses control signals indicating a request to read from a register, write to a register, and set, clear, or test a designator, and decodes the address received to select the appropriate storage location for the requested function.
摘要翻译： 总线架构包括地址线，数据线和控制信号，以允许处理器与VLSI门阵列通信。 地址线由VLSI门阵列解释，以根据从处理器接收的控制信号来选择驻留在VLSI门阵列上的多位寄存器或单位指示符。 VLSI门阵列上的双地址解码逻辑检测指示从寄存器读取，写入寄存器，设置，清除或测试指示符的请求的控制信号，并解码所接收的地址，以选择所请求的适当存储位置 功能。
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公开(公告)号：US5515507A
公开(公告)日：1996-05-07
申请号：US173317
申请日：1993-12-23
申请人： Larry L. Byers , Joseba M. De Subijana , Wayne A. Michaelson , Lloyd E. Thorsbakken , Howard H. Tran
发明人： Larry L. Byers , Joseba M. De Subijana , Wayne A. Michaelson , Lloyd E. Thorsbakken , Howard H. Tran
CPC分类号： G06F11/10
摘要： A bus architecture and associated circuitry for providing communication between processors and multiple gate arrays whereby the size of the data being transferred may be either full words of 32-bits or 36-bits per word, or half words of 16-bits or 18-bits per word. Parity generation logic operates on the data to be sent over the bus to generate a parity value from the correct data bits depending on the selected data word size. Parity checking logic operates on the data received from the bus to check the parity of the correct data bits depending on the selected data word size.
摘要翻译： 一种总线架构和相关电路，用于提供处理器与多个门阵列之间的通信，从而正在传送的数据的大小可以是每字32位或36位的全字，或16位或18位的半字 每个字 奇偶校验生成逻辑对要通过总线发送的数据进行操作，以根据所选择的数据字大小从正确的数据位生成奇偶校验值。 奇偶校验逻辑对从总线接收的数据进行操作，以根据所选择的数据字大小检查正确数据位的奇偶性。
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公开(公告)号：US5495598A
公开(公告)日：1996-02-27
申请号：US173598
申请日：1993-12-23
IPC分类号： G06F9/32 , G06F9/38 , G06F11/267 , G06F11/00 , H03M13/00
CPC分类号： G06F9/3804 , G06F11/2236 , G06F9/30058 , G06F9/30094
摘要： A method and apparatus for detecting stuck faults in a signal line used to communicate a branch condition for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby the branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation. The branch condition is sent to the microprocessor as a signal pulse for a specified duration at a particular time, rather than by changing the level of the signal, thereby allowing communication of the branch condition over only one signal line but still providing for detection of faults in the VSLI gate array or faults inherent in the signal line.
摘要翻译： 一种用于检测用于通过包含可编程微处理器的数据处理系统和由双向总线连接的多个VLSI门阵列来传送用于执行条件转移指令的分支条件的信号线中的卡死故障的方法和装置，由此分支条件是 从驻留在执行异步并在微处理器外部的VLSI门阵列上的存储位置获得。 分支条件与分支目标地址的获取和程序计数器的递增并行获取和评估。 微处理器根据分支条件评估的结果改变指令序列控制。 分支条件作为特定时间的指定持续时间的信号脉冲发送到微处理器，而不是通过改变信号的电平，从而允许在仅一条信号线上通信分支条件，但仍然提供故障的检测 在VSLI门阵列或信号线固有的故障。
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公开(公告)号：US4953167A
公开(公告)日：1990-08-28
申请号：US244190
申请日：1988-09-13
CPC分类号： G06F11/085
摘要： Logic checking circuits are provided for verifying whether or not the data bus enable logic circuits are operating properly in response to operational commands to transmit or to NOT transmit data. The transmit latches in the bus interface logic circuits are continuously monitored to determine if they are set or NOT set in a position to enable transmission of data or NOT to enable transmission of data to a bus. Transmit gating circuit means are couple to the output of said transmit latches for determining if all of the transmit latches are in the same state and are in the state ordered by the central controller, and for determining whether the state ordered by the central controller occurs in the exact time period during which the command to transmit should be executed.
摘要翻译： 逻辑检查电路被提供用于验证数据总线使能逻辑电路是否响应于要发送或不发送数据的操作命令而正常工作。 总线接口逻辑电路中的发送锁存器被连续地监视，以确定它们是被设置还是不被设置在能够传输数据或不使数据传输到总线的位置。 发送门控电路装置耦合到所述发送锁存器的输出端，用于确定所有发送锁存器是否处于相同状态并且处于由中央控制器排序的状态，并且用于确定由中央控制器排序的状态是否发生在 应执行发送命令的确切时间段。
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7.发明授权
公开(公告)号：US5539888A
公开(公告)日：1996-07-23
申请号：US369862
申请日：1995-01-06
CPC分类号： G06F9/30058 , G06F9/3877
摘要： A method and apparatus for executing conditional branch instructions by a data processing system containing a programmable microprocessor and multiple VLSI gate arrays connected by a bi-directional bus, whereby a branch condition is obtained from a storage location resident on a VLSI gate array executing asynchronous and external to the microprocessor. The branch condition is fetched and evaluated in parallel with the fetching of the branch target address and the incrementing of the program counter. The microprocessor changes instruction sequence control depending on the results of the branch condition evaluation.
摘要翻译： 一种用于通过包含可编程微处理器和由双向总线连接的多个VLSI门阵列的数据处理系统来执行条件转移指令的方法和装置，由此从驻留在执行异步的VLSI门阵列上的存储位置获得分支条件， 微处理器外部。 分支条件与分支目标地址的获取和程序计数器的递增并行获取和评估。 微处理器根据分支条件评估的结果改变指令序列控制。
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8.发明授权
公开(公告)号：US5488702A
公开(公告)日：1996-01-30
申请号：US233199
申请日：1994-04-26
CPC分类号： G06F11/1004
摘要： A system and method for detecting errors during the storage and retrieval of file information between a file cache system and a host computer system utilizes a block check sequence key as redundant data included in each block of file data transferred. The block check sequence key is generated by key generation logic and accompanies each block of file data stored in the file cache system by the host computer system. The block check sequence key is a compressed representation of the data within the selected block, as well as unique file and block identification information supplied by the requester of the write operation. When the block is retrieved from the file cache system, the system generates a new block check sequence key based on the data within the retrieved block and the unique file and block identification information supplied by the requester of the read operation. Validation logic ensures that if the retrieved key and the newly generated key does not match, an error signal is activated.
摘要翻译： 用于在文件高速缓存系统和主机系统之间的文件信息的存储和检索期间检测错误的系统和方法利用块校验序列密钥作为包含在传送的每个文件数据块中的冗余数据。 块检查序列密钥由密钥生成逻辑生成，并且由主计算机系统伴随存储在文件高速缓存系统中的每个文件数据块。 块检查序列密钥是所选块内的数据的压缩表示，以及由写操作的请求者提供的唯一的文件和块标识信息。 当从文件缓存系统检索到该块时，系统基于检索到的块内的数据和由读取操作的请求者提供的唯一文件和块识别信息生成新的块校验序列密钥。 验证逻辑确保如果检索到的密钥和新生成的密钥不匹配，则会激活错误信号。
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公开(公告)号：US5032984A
公开(公告)日：1991-07-16
申请号：US246509
申请日：1988-09-19
IPC分类号： G06F13/16
CPC分类号： G06F13/1647
摘要： A system for apportioning serially supplied data among eight contending memory banks tends to equalize usage among the banks despite their arrangement in a predetermined, sequential priority. Each bank has a data hold register, an OR logic gate to generate a request signal whenever its register contains data, and a negative AND gate for enabling the bank for clearing data from its register. All except the lowest priority bank further include a blocking latch and an enabling NOR gate. Each blocking latch is set when its associated bank is enabled, and then inhibits its associated AND gate and each higher priority AND gate, while enabling each lower priority NOR gate. Each enabled NOR gate provides an enabling signal to all lower priority AND gates. When the lowest priority AND gate is enabled by the NOR gates and its request signal, all blocking latches are cleared. The banks thus are utilized in a sequence that is maintained even if one or more banks are bypassed on occasion.
摘要翻译： 在八个竞争存储器组中用于分配串行提供的数据的系统倾向于使得各个存储体之间的使用相等，尽管它们以预定的顺序优先级排列。 每个存储体都有一个数据保持寄存器，一个OR逻辑门，每当其寄存器包含数据时产生请求信号，以及一个用于使该存储体从其寄存器中清除数据的负与门。 所有除最低优先级组之外的所有其他进一步包括阻塞锁存器和使能NOR门。 当其相关联的组使能时，每个阻塞锁存器被置1，然后禁止其相关联的与门和每个较高优先级的与门，同时使能每个较低优先级的或非门。 每个使能的或非门向所有较低优先级的与门提供使能信号。 当通过或非门及其请求信号使能最低优先级AND门时，所有阻塞锁存器被清零。 因此，即使有时候绕过一个或多个银行，银行也被维持在一个序列中。
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公开(公告)号：US5535405A
公开(公告)日：1996-07-09
申请号：US172657
申请日：1993-12-23
CPC分类号： G06F11/1637 , G06F11/1625 , G06F9/30036 , G06F9/3885
摘要： A microsequencer bus controller system provides a flexible and efficient mechanism for controlling multiple gate arrays called stations embedded within a larger computer system. A control store memory, loaded at system initialization time, holds fixed-length instructions simultaneously executed by dual reduced instruction set (RISC) microprocessors which interface with the multiple stations over a bi-directional bus. The master microprocessor compares the result of the processing of each instruction with the slave microprocessor's result to detect any differences, thereby minimizing error latency. Master and slave microprocessors each control half of the stations on the bus. Data widths of 32-bit and 36-bit words are supported by the microprocessors, bus, and stations.
摘要翻译： 微定序器总线控制器系统提供了一种灵活和有效的机制，用于控制被称为站内嵌入较大计算机系统的多个门阵列。 在系统初始化时刻加载的控制存储器存储由双精简指令集（RISC）微处理器同时执行的固定长度指令，它们通过双向总线与多个站进行接口。 主微处理器将每个指令的处理结果与从属微处理器的结果进行比较，以检测任何差异，从而最大限度地减少错误延迟。 主从微处理器控制总线上的一半站。 32位和36位字的数据宽度由微处理器，总线和站支持。
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