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公开(公告)号：US08063450B2
公开(公告)日：2011-11-22
申请号：US12441220
申请日：2007-09-19
申请人： Lars-Erik Wernersson , Erik Lind , Tomas Bryllert , Jonas Ohlsson , Truls Löwgren , Lars Samuelson , Claes Thelander
发明人： Lars-Erik Wernersson , Erik Lind , Tomas Bryllert , Jonas Ohlsson , Truls Löwgren , Lars Samuelson , Claes Thelander
IPC分类号： H01L27/088
CPC分类号： H01L27/0883 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/20 , H01L29/775 , H01L29/7828
摘要： The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.
摘要翻译： 本发明涉及具有封盖几何形状的垂直纳米线晶体管。 垂直纳米线晶体管的阈值电压由纳米线的直径，纳米线的掺杂，纳米线中的异质结构段的引入，纳米线周围的壳结构中的掺杂来调节，栅极的功函数 堆叠，通过应变工程，通过控制电介质或纳米线材料的选择。 具有不同阈值电压的晶体管设置在相同的基板上，这使得能够利用阈值电压的偏移设计高级电路，类似于直接耦合的场逻辑。
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公开(公告)号：US20100176459A1
公开(公告)日：2010-07-15
申请号：US12441220
申请日：2007-09-19
申请人： Lars-Erik Wernersson , Erik Lind , Tomas Bryllert , Jonas Ohlsson , Truls Löwgren , Lars Samuelson , Claes Thelander
发明人： Lars-Erik Wernersson , Erik Lind , Tomas Bryllert , Jonas Ohlsson , Truls Löwgren , Lars Samuelson , Claes Thelander
IPC分类号： H01L27/088 , H01L21/36
CPC分类号： H01L27/0883 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/20 , H01L29/775 , H01L29/7828
摘要： The present invention relates to vertical nanowire transistors with a wrap-gated geometry. The threshold voltage of the vertical nanowire transistors is controlled by the diameter of the nanowire, the doping of the nanowire, the introduction of segments of heterostructures in the nanowire, the doping in shell-structures surrounding the nanowire, tailoring the work function of the gate stack, by strain engineering, by control of the dielectrica or the choice of nanowire material. Transistors with varying threshold voltages are provided on the same substrate, which enables the design of advanced circuits utilizing the shifts in the threshold voltages, similar to the directly coupled field logic.
摘要翻译： 本发明涉及具有封盖几何形状的垂直纳米线晶体管。 垂直纳米线晶体管的阈值电压由纳米线的直径，纳米线的掺杂，纳米线中的异质结构段的引入，纳米线周围的壳结构中的掺杂来调节，栅极的功函数 堆叠，通过应变工程，通过控制电介质或纳米线材料的选择。 具有不同阈值电压的晶体管设置在相同的基板上，这使得能够利用阈值电压的偏移设计高级电路，类似于直接耦合的场逻辑。
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公开(公告)号：US20110140086A1
公开(公告)日：2011-06-16
申请号：US13003046
申请日：2009-07-02
IPC分类号： H01L29/775 , B82Y99/00
CPC分类号： H01L29/7881 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/42332 , H01L29/66825 , H01L29/803 , Y10S977/938
摘要： The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire (3) forming a current transport channel, one or more shell layers (4) arranged around at least a portion of the nanowire (3), and nano-sized charge trapping centres (10) embedded in said one or more shell layers (4), and one or more gate electrodes (14) arranged around at least a respective portion of said one or more shell layers (4). Preferably said one or more shell layers (4) are made of a wide band gap material or an insulator. The charge trapping centres (10) may be charged/written by using said one or more gate electrodes (14) and a change in an amount of charge stored in one or more of the charge trapping centres (10) alters the conductivity of the nanowire (3).
摘要翻译： 本发明提供一种纳米结构存储器件，其包括形成电流传输沟道的至少一个半导体纳米线（3），围绕至少一部分纳米线（3）布置的一个或多个壳层（4）和纳米尺寸的电荷俘获 嵌入在所述一个或多个壳层（4）中的中心（10）以及围绕至少所述一个或多个壳层（4）的相应部分布置的一个或多个栅电极（14）。 优选地，所述一个或多个壳层（4）由宽带隙材料或绝缘体制成。 可以通过使用所述一个或多个栅电极（14）对电荷捕获中心（10）进行充电/写入，并且存储在一个或多个电荷捕获中心（10）中的电荷量的变化改变了纳米线的导电性 （3）。
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公开(公告)号：US08212237B2
公开(公告)日：2012-07-03
申请号：US13003046
申请日：2009-07-02
IPC分类号： H01L31/00
CPC分类号： H01L29/7881 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/42332 , H01L29/66825 , H01L29/803 , Y10S977/938
摘要： The present invention provides a nanostructured memory device comprising at least one semiconductor nanowire (3) forming a current transport channel, one or more shell layers (4) arranged around at least a portion of the nanowire (3), and nano-sized charge trapping centers (10) embedded in said one or more shell layers (4), and one or more gate electrodes (14) arranged around at least a respective portion of said one or more shell layers (4). Preferably said one or more shell layers (4) are made of a wide band gap material or an insulator. The charge trapping centers (10) may be charged/written by using said one or more gate electrodes (14) and a change in an amount of charge stored in one or more of the charge trapping centers (10) alters the conductivity of the nanowire (3).
摘要翻译： 本发明提供一种纳米结构存储器件，其包括形成电流传输沟道的至少一个半导体纳米线（3），围绕至少一部分纳米线（3）布置的一个或多个壳层（4）和纳米尺寸的电荷俘获 嵌入在所述一个或多个壳层（4）中的中心（10）以及围绕至少所述一个或多个壳层（4）的相应部分布置的一个或多个栅电极（14）。 优选地，所述一个或多个壳层（4）由宽带隙材料或绝缘体制成。 可以通过使用所述一个或多个栅电极（14）对电荷捕获中心（10）进行充电/写入，并且存储在一个或多个电荷捕获中心（10）中的电荷量的变化改变了纳米线的导电性 （3）。
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公开(公告)号：US08143658B2
公开(公告)日：2012-03-27
申请号：US12450373
申请日：2008-03-26
申请人： Lars Samuelson , Claes Thelander
发明人： Lars Samuelson , Claes Thelander
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L29/7881 , B82Y10/00 , G11C13/025 , G11C2213/16 , H01L27/11521 , H01L27/1156 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66477 , H01L29/7888 , H01L29/792 , H01L29/7926 , Y10S977/936 , Y10S977/937 , Y10S977/938
摘要： The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established.
摘要翻译： 本发明涉及一种用于电荷存储的纳米结构装置。 特别地，本发明涉及一种可用于存储器应用的电荷存储装置。 根据本发明，该装置包括第一纳米线，其具有围绕其一部分长度布置的第一卷绕栅极和连接到一端的电荷存储端子，以及第二纳米线，其具有围绕其长度的一部分布置的第二卷绕栅极。 电荷存储端子连接到第二卷绕栅极，由此存储在电荷存储端子上的电荷可以影响第二纳米线中的电流。 电流可以与写入（充电）或未写入（无电荷）状态有关，因此建立了记忆功能。
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公开(公告)号：US20070206488A1
公开(公告)日：2007-09-06
申请号：US11359410
申请日：2006-02-23
申请人： Claes Thelander , Lars Samuelson
发明人： Claes Thelander , Lars Samuelson
IPC分类号： G11B5/00
CPC分类号： H01L29/8616 , B82Y10/00 , G11C16/02 , G11C2216/08 , H01L29/0665 , H01L29/0673 , H01L29/068 , Y10S977/902 , Y10S977/943
摘要： The present invention relates to a device for data storage. In particular the invention relates to a single electron memory device utilizing multiple tunnel junctions, and arrays or matrixes of such devices. The data storage device according to the invention comprises at least one nanowhisker adapted to store a charge. Each of the nanowhiskers comprises a sequence of axial segments of materials of different band gaps, arranged to provide a sequence of conductive islands separated by tunnel barriers and a storage island arranged at one end of the conductive island/tunnel barrier sequence, whereby to provide a data storage capability. The number of conductive islands should preferably be between five and ten.
摘要翻译： 本发明涉及一种用于数据存储的装置。 特别地，本发明涉及利用多个隧道结的单电子存储器件，以及这种器件的阵列或矩阵。 根据本发明的数据存储装置包括适于存储电荷的至少一个纳米晶须。 每个纳米晶须包括不同带隙的材料的轴向段的序列，其被布置成提供由隧道屏障隔开的一系列导电岛和布置在导电岛/隧道势垒序列的一端处的存储岛，由此提供 数据存储能力。 导电岛数应优选在5至10之间。
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公开(公告)号：US20110204331A1
公开(公告)日：2011-08-25
申请号：US12450373
申请日：2008-03-26
申请人： Lars Samuelson , Claes Thelander
发明人： Lars Samuelson , Claes Thelander
IPC分类号： H01L29/775
CPC分类号： H01L29/7881 , B82Y10/00 , G11C13/025 , G11C2213/16 , H01L27/11521 , H01L27/1156 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66477 , H01L29/7888 , H01L29/792 , H01L29/7926 , Y10S977/936 , Y10S977/937 , Y10S977/938
摘要： The present invention relates to a nanostructured device for charge storage. In particular the invention relates to a charge storage device that can be used for memory applications. According to the invention the device comprise a first nanowire with a first wrap gate arranged around a portion of its length, and a charge storing terminal connected to one end, and a second nanowire with a second wrap gate arranged around a portion of its length. The charge storing terminal is connected to the second wrap gate, whereby a charge stored on the charge storing terminal can affect a current in the second nanowire. The current can be related to written (charged) or unwritten (no charge) state, and hence a memory function is established.
摘要翻译： 本发明涉及一种用于电荷存储的纳米结构装置。 特别地，本发明涉及一种可用于存储器应用的电荷存储装置。 根据本发明，该装置包括第一纳米线，其具有围绕其一部分长度布置的第一卷绕栅极和连接到一端的电荷存储端子，以及第二纳米线，其具有围绕其长度的一部分布置的第二卷绕栅极。 电荷存储端子连接到第二卷绕栅极，由此存储在电荷存储端子上的电荷可以影响第二纳米线中的电流。 电流可以与写入（充电）或未写入（无电荷）状态有关，因此建立了记忆功能。
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公开(公告)号：US07826336B2
公开(公告)日：2010-11-02
申请号：US11359410
申请日：2006-02-23
申请人： Claes Thelander , Lars Samuelson
发明人： Claes Thelander , Lars Samuelson
IPC分类号： G11B5/00
CPC分类号： H01L29/8616 , B82Y10/00 , G11C16/02 , G11C2216/08 , H01L29/0665 , H01L29/0673 , H01L29/068 , Y10S977/902 , Y10S977/943
摘要： The present invention relates to a device for data storage. In particular the invention relates to a single electron memory device utilizing multiple tunnel junctions, and arrays or matrixes of such devices. The data storage device according to the invention comprises at least one nanowhisker adapted to store a charge. Each of the nanowhiskers comprises a sequence of axial segments of materials of different band gaps, arranged to provide a sequence of conductive islands separated by tunnel barriers and a storage island arranged at one end of the conductive island/tunnel barrier sequence, whereby to provide a data storage capability. The number of conductive islands should preferably be between five and ten.
摘要翻译： 本发明涉及一种用于数据存储的装置。 特别地，本发明涉及利用多个隧道结的单电子存储器件，以及这种器件的阵列或矩阵。 根据本发明的数据存储装置包括适于存储电荷的至少一个纳米晶须。 每个纳米晶须包括不同带隙的材料的轴向段的序列，其被布置成提供由隧道屏障隔开的一系列导电岛和布置在导电岛/隧道势垒序列的一端处的存储岛，由此提供 数据存储能力。 导电岛数应优选在5至10之间。
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