公开(公告)号：US20050235186A1

公开(公告)日：2005-10-20

申请号：US11151258

申请日：2005-06-14

申请人： Laung-Terng Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

发明人： Laung-Terng Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

公开(公告)号：US20090037786A1

公开(公告)日：2009-02-05

申请号：US12285225

申请日：2008-09-30

申请人： Laung-Terng Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

发明人： Laung-Terng Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

公开(公告)号：US07904773B2

公开(公告)日：2011-03-08

申请号：US12285269

申请日：2008-10-01

申请人： Laung-Terng (L. T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

发明人： Laung-Terng (L. T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

IPC分类号： G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

公开(公告)号：US20090070646A1

公开(公告)日：2009-03-12

申请号：US12285269

申请日：2008-10-01

申请人： Laung-Terng (L.T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

发明人： Laung-Terng (L.T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

IPC分类号： G01R31/3183 ,  G06F11/27 ,  G01R31/3187

CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

公开(公告)号：US06954887B2

公开(公告)日：2005-10-11

申请号：US10101517

申请日：2002-03-20

申请人： Laung-Terng (L.-T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

发明人： Laung-Terng (L.-T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

公开(公告)号：US07779323B2

公开(公告)日：2010-08-17

申请号：US12222931

申请日：2008-08-20

申请人： Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Hsin-Po Wang ,  Hao-Jan Chao ,  Xiaoqing Wen

发明人： Laung-Terng Wang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Hsin-Po Wang ,  Hao-Jan Chao ,  Xiaoqing Wen

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F17/5022 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/318594 ,  G06F17/5031 ,  G06F17/505

摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in an integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus allows generating and loading N pseudorandom or predetermined stimuli to all the scan cells within the N clock domains in the integrated circuit or circuit assembly during the shift operation, applying an ordered sequence of capture clocks to all the scan cells within the N clock domains during the capture operation, compacting or comparing N output responses of all the scan cells for analysis during the compact/compare operation, and repeating the above process until a predetermined limiting criteria is reached. A computer-aided design (CAD) system is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的故障，以及跨越自检或扫描测试模式的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1且每个域具有 多个扫描单元。 该方法和装置允许在移位操作期间将N个伪随机数或预定刺激生成并加载到集成电路或电路组件中的N个时钟域内的所有扫描单元，向N中的所有扫描单元应用捕获时钟的有序序列 捕获操作期间的时钟域，压缩或比较所有扫描单元的N个输出响应，以便在紧凑/比较操作期间进行分析，并重复上述处理，直到达到预定的限制标准。 进一步开发了计算机辅助设计（CAD）系统来实现该方法并综合了该装置。

公开(公告)号：US07191373B2

公开(公告)日：2007-03-13

申请号：US10086214

申请日：2002-02-27

申请人： Laung-Terng (L.-T.) Wang ,  Ming-Tung Chang ,  Shyh-Horng Lin ,  Hao-Jan Chao ,  Jaehee Lee ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Sen-Wei Tsai ,  Chi-Chan Hsu

发明人： Laung-Terng (L.-T.) Wang ,  Ming-Tung Chang ,  Shyh-Horng Lin ,  Hao-Jan Chao ,  Jaehee Lee ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Sen-Wei Tsai ,  Chi-Chan Hsu

IPC分类号： G01R31/28

CPC分类号： G01R31/3185 ,  G01R31/31704 ,  G01R31/31705

摘要： A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

摘要翻译： 一种用于在集成电路中插入设计调试（DFD）电路以调试或诊断DFT模块（包括扫描核心），存储器BIST（内置自检）内核，逻辑BIST核心和功能核心的方法和装置。 本发明还包括使用DFD控制器来执行多个DFD命令来调试或诊断嵌入在DFD电路中的DFT模块。 当单独使用或组合在一起时，这些DFD命令将使用低成本DFT调试器在评估板或系统上的集成电路中的DFT模块中检测或定位物理故障。 根据IEEE 1149.1边界扫描标准，进一步开发了一种计算机辅助设计（CAD）方法来合成DFD控制器和DFD电路。 DFD控制器支持但不限于以下DFD命令：RUN_SCAN，RUN_MBIST，RUN_LBIST，DBG_SCAN，DBG_MBIST，DBG_LBIST，DBG_FUNCTION，SELECT，SHIFT，SHIFT_CHAIN，CAPTURE，RESET，BREAK，RUN，STEP和STOP。

公开(公告)号：US07444567B2

公开(公告)日：2008-10-28

申请号：US10406592

申请日：2003-04-04

申请人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

发明人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

IPC分类号： G01R31/28

CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

公开(公告)号：US20090235132A1

公开(公告)日：2009-09-17

申请号：US12468909

申请日：2009-05-20

申请人： Laung-Terng Wang ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Meng-Chyi Lin ,  Shyh-Horng Lin ,  Ta-Chia Yeh ,  Sen-Wei Tsai ,  Khader S. Abdel-Hafez

发明人： Laung-Terng Wang ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Meng-Chyi Lin ,  Shyh-Horng Lin ,  Ta-Chia Yeh ,  Sen-Wei Tsai ,  Khader S. Abdel-Hafez

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318547 ,  G01R31/318591

摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

摘要翻译： 用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。 基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。 广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。 虚拟扫描控制器控制广播机构的操作。 系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。 进一步提出了方法来重新排列所选扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。

公开(公告)号：US07552373B2

公开(公告)日：2009-06-23

申请号：US10339667

申请日：2003-01-10

申请人： Laung-Terng Wang ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Meng-Chyi Lin ,  Shyh-Horng Lin ,  Ta-Chia Yeh ,  Sen-Wei Tsai ,  Khader S. Abdel-Hafez

发明人： Laung-Terng Wang ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Meng-Chyi Lin ,  Shyh-Horng Lin ,  Ta-Chia Yeh ,  Sen-Wei Tsai ,  Khader S. Abdel-Hafez

IPC分类号： G01R31/28

CPC分类号： G01R31/31926 ,  G01R31/318533

摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.

摘要翻译： 用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。 基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。 广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。 虚拟扫描控制器控制广播机构的操作。 系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。 进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。