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    Multiple-capture DFT system for scan-based integrated circuits
    2.
    发明授权
    Multiple-capture DFT system for scan-based integrated circuits 有权
    用于基于扫描的集成电路的多捕捉DFT系统

    公开(公告)号：US07904773B2

    公开(公告)日：2011-03-08

    申请号：US12285269

    申请日：2008-10-01

    申请人： Laung-Terng (L. T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    发明人： Laung-Terng (L. T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

    摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

    摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

    Method and apparatus for unifying self-test with scan-test during prototype debug and production test
    3.
    发明授权
    Method and apparatus for unifying self-test with scan-test during prototype debug and production test 失效
    在原型调试和生产测试过程中用扫描测试统一自检的方法和装置

    公开(公告)号：US07444567B2

    公开(公告)日：2008-10-28

    申请号：US10406592

    申请日：2003-04-04

    申请人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

    发明人： Laung-Terng (L.-T.) Wang ,  Xiaoqing Wen ,  Khader S. Abdel-Hafez ,  Shyh-Horng Lin ,  Hsin-Po Wang ,  Ming-Tung Chang ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Chi-Chan Hsu

    IPC分类号： G01R31/28

    CPC分类号： G06F11/27 ,  G01R31/318586 ,  G01R31/318594

    摘要： A method and apparatus for testing or diagnosing faults in a scan-based integrated circuit using a unified self-test and scan-test technique. The method and apparatus comprises using a unified test controller to ease prototype debug and production test. The unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self-test or scan-test. The capture clocks generated by the capture clock generator are used to guide at-speed or reduced-speed self-test (or scan-test) within each clock domain. The frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains. This unified approach allows designers to test or diagnose stuck-type and non-stuck-type faults with a low-cost DFT (design-for-test) tester or a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus.

    摘要翻译： 一种用于使用统一的自检和扫描测试技术来测试或诊断基于扫描的集成电路中的故障的方法和装置。 该方法和装置包括使用统一的测试控制器来简化原型调试和生产测试。 统一的测试控制器还包括使用捕获时钟发生器和每个嵌入在时钟域中的多个域时钟发生器来执行自检或扫描测试。 由捕获时钟发生器产生的捕获时钟用于引导每个时钟域内的速度或速度自检（或扫描测试）。 这些捕获时钟的频率与控制时钟域的系统时钟的频率完全无关。 这种统一的方法允许设计人员使用低成本DFT（设计测试）测试仪或低成本DFT调试器来测试或诊断卡住型和非卡住型故障。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。

    Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques
    4.
    发明授权
    Method and apparatus for diagnosing failures in an integrated circuit using design-for-debug (DFD) techniques 有权
    使用设计调试（DFD）技术诊断集成电路故障的方法和装置

    公开(公告)号：US07191373B2

    公开(公告)日：2007-03-13

    申请号：US10086214

    申请日：2002-02-27

    申请人： Laung-Terng (L.-T.) Wang ,  Ming-Tung Chang ,  Shyh-Horng Lin ,  Hao-Jan Chao ,  Jaehee Lee ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Sen-Wei Tsai ,  Chi-Chan Hsu

    发明人： Laung-Terng (L.-T.) Wang ,  Ming-Tung Chang ,  Shyh-Horng Lin ,  Hao-Jan Chao ,  Jaehee Lee ,  Hsin-Po Wang ,  Xiaoqing Wen ,  Po-Ching Hsu ,  Shih-Chia Kao ,  Meng-Chyi Lin ,  Sen-Wei Tsai ,  Chi-Chan Hsu

    IPC分类号： G01R31/28

    CPC分类号： G01R31/3185 ,  G01R31/31704 ,  G01R31/31705

    摘要： A method and apparatus for inserting design-for-debug (DFD) circuitries in an integrated circuit to debug or diagnose DFT modules, including scan cores, memory BIST (built-in self-test) cores, logic BIST cores, and functional cores. The invention further comprises using a DFD controller for executing a plurality of DFD commands to debug or diagnosis the DFT modules embedded with the DFD circuitries. When used alone or combined together, these DFD commands will detect or locate physical failures in the DFT modules in the integrated circuit on an evaluation board or system using a low-cost DFT debugger. A computer-aided design (CAD) method is further developed to synthesize the DFD controller and DFD circuitries according to the IEEE 1149.1 Boundary-scan Std. The DFD controller supports, but is not limited to, the following DFD commands: RUN_SCAN, RUN_MBIST, RUN_LBIST, DBG_SCAN, DBG_MBIST, DBG_LBIST, DBG_FUNCTION, SELECT, SHIFT, SHIFT_CHAIN, CAPTURE, RESET, BREAK, RUN, STEP, and STOP.

    摘要翻译： 一种用于在集成电路中插入设计调试（DFD）电路以调试或诊断DFT模块（包括扫描核心），存储器BIST（内置自检）内核，逻辑BIST核心和功能核心的方法和装置。 本发明还包括使用DFD控制器来执行多个DFD命令来调试或诊断嵌入在DFD电路中的DFT模块。 当单独使用或组合在一起时，这些DFD命令将使用低成本DFT调试器在评估板或系统上的集成电路中的DFT模块中检测或定位物理故障。 根据IEEE 1149.1边界扫描标准，进一步开发了一种计算机辅助设计（CAD）方法来合成DFD控制器和DFD电路。 DFD控制器支持但不限于以下DFD命令：RUN_SCAN，RUN_MBIST，RUN_LBIST，DBG_SCAN，DBG_MBIST，DBG_LBIST，DBG_FUNCTION，SELECT，SHIFT，SHIFT_CHAIN，CAPTURE，RESET，BREAK，RUN，STEP和STOP。

    Multiple-Capture DFT system for scan-based integrated circuits
    5.
    发明申请
    Multiple-Capture DFT system for scan-based integrated circuits 有权
    用于基于扫描的集成电路的多捕获DFT系统

    公开(公告)号：US20090070646A1

    公开(公告)日：2009-03-12

    申请号：US12285269

    申请日：2008-10-01

    申请人： Laung-Terng (L.T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    发明人： Laung-Terng (L.T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    IPC分类号： G01R31/3183 ,  G06F11/27 ,  G01R31/3187

    CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

    摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

    摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

    Multiple-capture DFT system for scan-based integrated circuits
    6.
    发明申请
    Multiple-capture DFT system for scan-based integrated circuits 失效
    用于基于扫描的集成电路的多捕捉DFT系统

    公开(公告)号：US20050235186A1

    公开(公告)日：2005-10-20

    申请号：US11151258

    申请日：2005-06-14

    申请人： Laung-Terng Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    发明人： Laung-Terng Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

    CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

    摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

    摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

    COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL
    9.
    发明申请
    COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL 失效
    计算机辅助设计系统，用于自动扫描合成记录级别

    公开(公告)号：US20120246604A1

    公开(公告)日：2012-09-27

    申请号：US13490721

    申请日：2012-06-07

    申请人： Laung-Terng (L. -T.) WANG ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horag Lin ,  Hsin-Po Wang

    发明人： Laung-Terng (L. -T.) WANG ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horag Lin ,  Hsin-Po Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G01R31/31704 ,  G01R31/318314 ,  G01R31/318364 ,  G01R31/318583 ,  G01R31/318594 ,  G06F17/5022 ,  G06F17/5027 ,  G06F17/5045 ,  G06F2217/14

    摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

    摘要翻译： 一种在寄存器传输级（RTL）下自动扫描合成的方法和系统。 该方法和系统将产生在RTL建模的扫描HDL代码，用于在RTL建模的集成电路。 该方法和系统包括执行RTL可测试性分析，时钟域最小化，扫描选择，测试点选择，扫描修复和测试点插入，扫描替换和扫描拼接，扫描提取，交互式扫描调试，交互式扫描修复的计算机实现步骤 和冲洗/随机测试台生成。 此外，本发明还包括通过逐个模块执行扫描合成然后将这些扫描的模块拼接在一起的层次扫描合成的方法和系统。 本发明还包括将扫描HDL码与其他测试（DFT）HDL码进行集成和验证，包括边界扫描和逻辑BIST（内置自检）。