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    Multiple-capture DFT system for scan-based integrated circuits
    2.
    发明授权
    Multiple-capture DFT system for scan-based integrated circuits 有权
    用于基于扫描的集成电路的多捕捉DFT系统

    公开(公告)号：US07904773B2

    公开(公告)日：2011-03-08

    申请号：US12285269

    申请日：2008-10-01

    申请人： Laung-Terng (L. T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    发明人： Laung-Terng (L. T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    IPC分类号： G01R31/28

    CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

    摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

    摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

    Multiple-Capture DFT system for scan-based integrated circuits
    3.
    发明申请
    Multiple-Capture DFT system for scan-based integrated circuits 有权
    用于基于扫描的集成电路的多捕获DFT系统

    公开(公告)号：US20090070646A1

    公开(公告)日：2009-03-12

    申请号：US12285269

    申请日：2008-10-01

    申请人： Laung-Terng (L.T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    发明人： Laung-Terng (L.T.) Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    IPC分类号： G01R31/3183 ,  G06F11/27 ,  G01R31/3187

    CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

    摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

    摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

    Multiple-capture DFT system for scan-based integrated circuits
    4.
    发明申请
    Multiple-capture DFT system for scan-based integrated circuits 失效
    用于基于扫描的集成电路的多捕捉DFT系统

    公开(公告)号：US20050235186A1

    公开(公告)日：2005-10-20

    申请号：US11151258

    申请日：2005-06-14

    申请人： Laung-Terng Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    发明人： Laung-Terng Wang ,  Meng-Chyi Lin ,  Xiaoqing Wen ,  Hsin-Po Wang ,  Chi-Chan Hsu ,  Shih-Chia Kao ,  Fei-Sheng Hsu

    IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

    CPC分类号： G01R31/318594 ,  G01R31/31704 ,  G01R31/318552 ,  G01R31/31858

    摘要： A method and apparatus for providing ordered capture clocks to detect or locate faults within N clock domains and faults crossing any two clock domains in a scan-based integrated circuit or circuit assembly in self-test or scan-test mode, where N>1 and each domain has a plurality of scan cells. The method and apparatus will apply an ordered sequence of capture clocks to all scan cells within N clock domains where one or more capture clocks must contain one or more shift clock pulses during the capture operation. A computer-aided design (CAD) method is further developed to realize the method and synthesize the apparatus. In order to further improve the circuit's fault coverage, a CAD method and apparatus are further developed to minimize the memory usage and generate scan patterns for full-scan and feed-forward partial-scan designs containing transparent storage cells, asynchronous set/reset signals, tri-state busses, and low-power gated clocks.

    摘要翻译： 一种用于提供有序捕获时钟以检测或定位N个时钟域内的故障的方法和装置，以及在自检或扫描测试模式中跨过基于扫描的集成电路或电路组件中的任何两个时钟域的故障，其中N≥1和 每个域具有多个扫描单元。 该方法和装置将对N个时钟域内的所有扫描单元应用有序序列的捕获时钟，其中一个或多个捕获时钟在捕获操作期间必须包含一个或多个移位时钟脉冲。 进一步开发了计算机辅助设计（CAD）方法，实现了该方法并综合了该装置。 为了进一步改善电路的故障覆盖范围，进一步开发了一种CAD方法和装置，以最小化存储器使用并产生包含透明存储单元，异步设置/复位信号的全扫描和前馈部分扫描设计的扫描模式， 三态总线和低功率门控时钟。

    COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL
    6.
    发明申请
    COMPUTER-AIDED DESIGN SYSTEM TO AUTOMATE SCAN SYNTHESIS AT REGISTER-TRANSFER LEVEL 失效
    计算机辅助设计系统，用于自动扫描合成记录级别

    公开(公告)号：US20120246604A1

    公开(公告)日：2012-09-27

    申请号：US13490721

    申请日：2012-06-07

    申请人： Laung-Terng (L. -T.) WANG ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horag Lin ,  Hsin-Po Wang

    发明人： Laung-Terng (L. -T.) WANG ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horag Lin ,  Hsin-Po Wang

    IPC分类号： G06F17/50

    CPC分类号： G06F17/505 ,  G01R31/31704 ,  G01R31/318314 ,  G01R31/318364 ,  G01R31/318583 ,  G01R31/318594 ,  G06F17/5022 ,  G06F17/5027 ,  G06F17/5045 ,  G06F2217/14

    摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

    摘要翻译： 一种在寄存器传输级（RTL）下自动扫描合成的方法和系统。 该方法和系统将产生在RTL建模的扫描HDL代码，用于在RTL建模的集成电路。 该方法和系统包括执行RTL可测试性分析，时钟域最小化，扫描选择，测试点选择，扫描修复和测试点插入，扫描替换和扫描拼接，扫描提取，交互式扫描调试，交互式扫描修复的计算机实现步骤 和冲洗/随机测试台生成。 此外，本发明还包括通过逐个模块执行扫描合成然后将这些扫描的模块拼接在一起的层次扫描合成的方法和系统。 本发明还包括将扫描HDL码与其他测试（DFT）HDL码进行集成和验证，包括边界扫描和逻辑BIST（内置自检）。

    Computer-aided design system to automate scan synthesis at register-transfer level
    8.
    发明授权
    Computer-aided design system to automate scan synthesis at register-transfer level 失效
    计算机辅助设计系统，用于在寄存器传输级别自动扫描合成

    公开(公告)号：US06957403B2

    公开(公告)日：2005-10-18

    申请号：US10108238

    申请日：2002-03-28

    申请人： Laung-Terng Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-P Wang

    发明人： Laung-Terng Wang ,  Augusli Kifli ,  Fei-Sheng Hsu ,  Shih-Chia Kao ,  Xiaoqing Wen ,  Shyh-Horng Lin ,  Hsin-P Wang

    IPC分类号： G01R31/317 ,  G01R31/3183 ,  G01R31/3185 ,  G06F17/50 ,  G06F19/00

    CPC分类号： G06F17/505 ,  G01R31/31704 ,  G01R31/318314 ,  G01R31/318364 ,  G01R31/318583 ,  G01R31/318594 ,  G06F17/5022 ,  G06F17/5027 ,  G06F17/5045 ,  G06F2217/14

    摘要： A method and system to automate scan synthesis at register-transfer level (RTL). The method and system will produce scan HDL code modeled at RTL for an integrated circuit modeled at RTL. The method and system comprise computer-implemented steps of performing RTL testability analysis, clock-domain minimization, scan selection, test point selection, scan repair and test point insertion, scan replacement and scan stitching, scan extraction, interactive scan debug, interactive scan repair, and flush/random test bench generation. In addition, the present invention further comprises a method and system for hierarchical scan synthesis by performing scan synthesis module-by-module and then stitching these scanned modules together at top-level. The present invention further comprises integrating and verifying the scan HDL code with other design-for-test (DFT) HDL code, including boundary-scan and logic BIST (built-in self-test).

    摘要翻译： 一种在寄存器传输级（RTL）下自动扫描合成的方法和系统。 该方法和系统将产生在RTL建模的扫描HDL代码，用于在RTL建模的集成电路。 该方法和系统包括执行RTL可测试性分析，时钟域最小化，扫描选择，测试点选择，扫描修复和测试点插入，扫描替换和扫描拼接，扫描提取，交互式扫描调试，交互式扫描修复的计算机实现步骤 和冲洗/随机测试台生成。 此外，本发明还包括通过逐个模块执行扫描合成然后将这些扫描的模块拼接在一起的层次扫描合成的方法和系统。 本发明还包括将扫描HDL码与其他测试（DFT）HDL码进行集成和验证，包括边界扫描和逻辑BIST（内置自检）。

    Event-driven emulation system
    9.
    发明授权
    Event-driven emulation system 有权
    事件驱动仿真系统

    公开(公告)号：US07970597B2

    公开(公告)日：2011-06-28

    申请号：US12120895

    申请日：2008-05-15

    申请人： Meng-Chyi Lin ,  Fei-Sheng Hsu ,  Sweyyan Shei

    发明人： Meng-Chyi Lin ,  Fei-Sheng Hsu ,  Sweyyan Shei

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5027 ,  G06F11/261

    摘要： A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources. Communicating with the resource interface circuit and the logic analyzer via a packet routing network, the debugger acquires and processes the data stored by the resource interface circuit and transmits commands to the resource interface circuit and the logic analyzer specifying clocking system operating characteristics, controlling signal data transfer to the debugger, and defining the signal events the logic analyzer is to detect.

    摘要翻译： 电路仿真器包括被编程为仿真电路的仿真资源，用于由仿真资源实现的时钟逻辑的时钟系统，资源接口电路，逻辑分析器和调试器。 资源接口电路向仿真资源提供输入信号，存储表示响应于输入信号产生的仿真资源产生的信号的行为的数据，并配置计时系统的操作特性。 在检测到所选择的仿真资源信号中的指定事件时，逻辑分析器断言触发信号，告诉时钟系统停止对仿真资源的计时。 通过分组路由网络与资源接口电路和逻辑分析仪进行通信，调试器获取并处理资源接口电路存储的数据，并向资源接口电路和逻辑分析仪发送命令，指定时钟系统的运行特性，控制信号数据 传输到调试器，并定义逻辑分析仪要检测的信号事件。

    EVENT-DRIVEN EMULATION SYSTEM
    10.
    发明申请
    EVENT-DRIVEN EMULATION SYSTEM 有权
    事件驱动仿真系统

    公开(公告)号：US20090287468A1

    公开(公告)日：2009-11-19

    申请号：US12120895

    申请日：2008-05-15

    申请人： Meng-Chyi Lin ,  Fei-Sheng Hsu ,  Sweyyan Shei

    发明人： Meng-Chyi Lin ,  Fei-Sheng Hsu ,  Sweyyan Shei

    IPC分类号： G06F9/455

    CPC分类号： G06F17/5027 ,  G06F11/261

    摘要： A circuit emulator includes emulation resources programmed to emulate a circuit, a clocking system for clocking logic implemented by the emulation resources, a resource interface circuit, a logic analyzer, and a debugger. The resource interface circuit supplies input signals to the emulation resources, stores data representing behavior of signals generated by the emulation resources produces in response to the input signals and configures operating characteristics of the clocking system. Upon detecting a specified event in the selected signals of the emulation resources, the logic analyzer asserts a trigger signal telling the clocking system to stop clocking the emulation resources. Communicating with the resource interface circuit and the logic analyzer via a packet routing network, the debugger acquires and processes the data stored by the resource interface circuit and transmits commands to the resource interface circuit and the logic analyzer specifying clocking system operating characteristics, controlling signal data transfer to the debugger, and defining the signal events the logic analyzer is to detect.

    摘要翻译： 电路仿真器包括被编程为仿真电路的仿真资源，用于由仿真资源实现的时钟逻辑的时钟系统，资源接口电路，逻辑分析器和调试器。 资源接口电路向仿真资源提供输入信号，存储表示响应于输入信号产生的仿真资源产生的信号的行为的数据，并配置计时系统的操作特性。 在检测到所选择的仿真资源信号中的指定事件时，逻辑分析器断言触发信号，告诉时钟系统停止对仿真资源的计时。 通过分组路由网络与资源接口电路和逻辑分析仪进行通信，调试器获取并处理资源接口电路存储的数据，并向资源接口电路和逻辑分析仪发送命令，指定时钟系统的运行特性，控制信号数据 传输到调试器，并定义逻辑分析仪要检测的信号事件。