公开(公告)号：US07697319B2

公开(公告)日：2010-04-13

申请号：US11706865

申请日：2007-02-14

Applicant: Laurent Dedieu ,  Sebastien Lefebvre

Inventor： Laurent Dedieu ,  Sebastien Lefebvre

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H03K3/356008 ,  H03K3/356104

Abstract: An embodiment of a device for memorization of a memory bit is provided, comprising a bistable circuit having complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit and following said preload phase, to go into a second state controlling setting up of said memory bit and its complement at said read/write terminals.

Abstract translation: 提供了用于存储存储器位的器件的实施例，其包括具有互补的第一和第二读/写端子的双稳态电路，其中该器件包括连接到所述双稳态电路的初始化输入，所述输入被设计成进入第一 状态控制所述双稳态电路的预加载阶段并且遵循所述预加载阶段，以进入控制在所述读/写端子处对所述存储器位及其补码进行设置的第二状态。

公开(公告)号：US20070211520A1

公开(公告)日：2007-09-13

申请号：US11706865

申请日：2007-02-14

Applicant: Laurent Dedieu ,  Sebastien Lefebvre

Inventor： Laurent Dedieu ,  Sebastien Lefebvre

IPC: G11C11/00

CPC classification number: G11C11/412 ,  H03K3/356008 ,  H03K3/356104

Abstract: An embodiment of the invention relates to a device for memorisation of a memory bit, provided with a bistable circuit with complementary first and second read/write terminals, wherein the device comprises an initialization input connected to said bistable circuit, said input being designed to go into a first state controlling a pre-load phase of said bistable circuit and following said preload phase, to go into a second state controlling setting up of said memory bit and its complement at said read/write terminals.

Abstract translation: 本发明的一个实施例涉及一种用于存储存储器位的装置，其具有互补的第一和第二读/写端子的双稳态电路，其中所述器件包括连接到所述双稳态电路的初始化输入，所述输入被设计为去 控制所述双稳态电路的预加载阶段并遵循所述预加载阶段的第一状态进入控制在所述读/写端子处所述存储器位及其补码的设置的第二状态。

公开(公告)号：US20120120716A1

公开(公告)日：2012-05-17

申请号：US13294843

申请日：2011-11-11

Applicant: Philippe Candelier ,  Laurent Dedieu ,  Noureddine Larhriq

Inventor： Philippe Candelier ,  Laurent Dedieu ,  Noureddine Larhriq

IPC: G11C11/00

CPC classification number: G11C11/419 ,  G11C7/24 ,  G11C8/20 ,  G11C11/41 ,  G11C16/22

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

Abstract translation: 安全存储器包括具有编程的启动状态的双稳态存储单元，以及用于响应于翻转信号翻转单元的状态的装置。 存储器可以包括用于以例如小于发射显微镜的获取时间的周期产生翻转信号的时钟。

公开(公告)号：US08432726B2

公开(公告)日：2013-04-30

申请号：US13294843

申请日：2011-11-11

Applicant: Philippe Candelier ,  Laurent Dedieu ,  Noureddine Larhriq

Inventor： Philippe Candelier ,  Laurent Dedieu ,  Noureddine Larhriq

IPC: G11C11/00

CPC classification number: G11C11/419 ,  G11C7/24 ,  G11C8/20 ,  G11C11/41 ,  G11C16/22

Abstract: A secure memory includes a bistable memory cell having a programmed start-up state, and means for flipping the state of the cell in response to a flip signal. The memory may include a clock for generating the flip signal with a period, for example, smaller than the acquisition time of an emission microscope.

Abstract translation: 安全存储器包括具有编程的启动状态的双稳态存储单元，以及用于响应于翻转信号翻转单元的状态的装置。 存储器可以包括用于以例如小于发射显微镜的获取时间的周期产生翻转信号的时钟。