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1.发明授权Time division multiplexed, piloted current monitoring in a switched mode DC—DC voltage converter and phase current measurement calibration for a multiphase converter 失效时分复用，开关模式DC-DC电压转换器中的导频电流监测和多相转换器的相电流测量校准公开(公告)号：US06906536B2
公开(公告)日：2005-06-14
申请号：US10720794
申请日：2003-11-24
CPC分类号： H02M3/1588 , G01R31/40 , H02M2001/0009 , Y02B70/1466
摘要： An arrangement for measuring current through a phase section of a buck mode DC-DC converter includes an auxiliary integrated circuit containing an auxiliary power MOSFET and a pilot MOSFET coupled in parallel with a current path through a high side MOSFET of a half-bridge of the converter. The pilot MOSFET has a current path coupled to a current measurement terminal. The MOSFETs of the auxiliary circuit are time division multiplexed with the high side MOSFET, whereby a determination of current through the auxiliary high side MOSFET is based upon current through the pilot device and the geometric ratio of the size of the pilot device to that of the high side auxiliary MOSFET. The high side MOSFET is activated for a large number of switching cycles relative to the pilot circuitry, but the pilot circuitry is activated sufficiently often to derive a relatively accurate measure of current flow.
摘要翻译： 用于测量通过降压模式DC-DC转换器的相位部分的电流的装置包括辅助集成电路，其包含辅助功率MOSFET和引导MOSFET，所述辅助功率MOSFET和引导MOSFET与通过半桥的高侧MOSFET的电流路径并联耦合 转换器。 导频MOSFET具有耦合到电流测量端子的电流路径。 辅助电路的MOSFET与高侧MOSFET进行时分多路复用，由此，通过辅助高侧MOSFET的电流的确定是基于通过导频装置的电流，以及导频装置的尺寸与 高边辅助MOSFET。 高边MOSFET相对于导频电路被激活大量的开关周期，但导频电路被充分激活，以导出电流的相对精确的测量。
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公开(公告)号：US06819190B2
公开(公告)日：2004-11-16
申请号：US10315836
申请日：2002-12-10
IPC分类号： H03B2700
CPC分类号： H03L7/0805 , H03K5/06 , H03K7/08 , H03L7/0812
摘要： A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an ‘open-loop’ tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.
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公开(公告)号：US5644309A
公开(公告)日：1997-07-01
申请号：US419610
申请日：1995-04-10
摘要： Method and apparatus for testing electrical devices which generate digital signals from analog signals applied to the devices. The testing determines whether or not the electrical devices are capable of properly generating all the different digital codes that correspond to the different analog signals in a particular bandwidth. The method and apparatus provide an external signal indicating whether an electrical device being tested functions properly.
摘要翻译： 用于测试从施加到设备的模拟信号产生数字信号的电子设备的方法和装置。 该测试确定电子设备是否能够适当地产生与特定带宽中的不同模拟信号相对应的所有不同的数字代码。 该方法和装置提供一个外部信号，指示被测电器是否正常工作。
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