公开(公告)号：US20080315329A1

公开(公告)日：2008-12-25

申请号：US12037569

申请日：2008-02-26

申请人： MICHAEL DAVID CHURCH ,  Alexander Kalnitsky ,  Lawrence George Pearce ,  Michael Ray Jayne ,  Thomas Andrew Jochum

发明人： MICHAEL DAVID CHURCH ,  Alexander Kalnitsky ,  Lawrence George Pearce ,  Michael Ray Jayne ,  Thomas Andrew Jochum

IPC分类号： H01L27/06

CPC分类号： H01L27/0629 ,  H01L27/0255 ,  H01L27/0814

摘要： An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.

摘要翻译： 集成电路包括并联连接的第一和第二二极管。 第一二极管具有第一击穿电压，并且在衬底的衬底的表面处具有彼此相邻的第一P型区域和第一N型区域，以形成横向二极管。 第二二极管具有小于第一击穿电压的第二击穿电压，并且在衬底中具有彼此相邻的第二P型区域和第二N型区域，以在表面下方形成横向二极管。第一和第二N型区域重叠 并且第一和第二P型区域电连接，由此第一和第二二极管是并联的。

公开(公告)号：US20080150358A1

公开(公告)日：2008-06-26

申请号：US12041503

申请日：2008-03-03

申请人： Lawrence George Pearce

发明人： Lawrence George Pearce

IPC分类号： H02J1/10

CPC分类号： H02M3/1584 ,  H02M2001/008 ,  Y10T307/305 ,  Y10T307/352 ,  Y10T307/391 ,  Y10T307/406 ,  Y10T307/414 ,  Y10T307/747 ,  Y10T307/76 ,  Y10T307/865 ,  Y10T307/944

摘要： A apparatus and method of operating a power converter circuit is provided. The method selectively couples control signals to at least one output driver stage of a plurality of output driver stages of the power converter circuit to obtain a desired output at a select output port of the plurality of output ports. Wherein each output driver stage has a defined current drive capacity that is output to the select output port in response to the control signals.

摘要翻译： 提供了一种操作电源转换器电路的装置和方法。 该方法将控制信号选择性地耦合到功率转换器电路的多个输出驱动级的至少一个输出驱动级，以在多个输出端口的选择输出端口处获得期望的输出。 其中每个输出驱动级具有定义的当前驱动能力，其响应于控制信号被输出到选择输出端口。

公开(公告)号：US07345378B2

公开(公告)日：2008-03-18

申请号：US11006006

申请日：2004-12-07

申请人： Lawrence George Pearce

发明人： Lawrence George Pearce

IPC分类号： H02J1/10 ,  H03K19/094 ,  H03K19/082

CPC分类号： H02M3/1584 ,  H02M2001/008 ,  Y10T307/305 ,  Y10T307/352 ,  Y10T307/391 ,  Y10T307/406 ,  Y10T307/414 ,  Y10T307/747 ,  Y10T307/76 ,  Y10T307/865 ,  Y10T307/944

摘要： A power supply circuit contains a plurality of DC-DC converter control loops that provide respectively different control signals. A plurality of output driver stages of given current drive capabilities have their inputs programmably connectable via a set of switches to control signals that may be generated by any of the converter control loops. The output of each output driver stage is externally selectively connectable to any of plural output voltage ports, so that each output voltage port is capable of supplying any of the respectively different output voltages associated with the voltage control signals generated by the DC-DC converter control loops, and has an output current capability that depends upon which output driver stages are coupled to it.

摘要翻译： 电源电路包含分别提供不同控制信号的多个DC-DC转换器控制回路。 具有给定电流驱动能力的多个输出驱动器级具有可编程地通过一组开关连接到可以由任何转换器控制回路产生的信号的输入。 每个输出驱动级的输出从外部可选择性地连接到多个输出电压端口中的任何一个，使得每个输出电压端口能够提供与由DC-DC转换器控制产生的电压控制信号相关联的分别不同的输出电压中的任何一个 并且具有取决于哪个输出驱动级与其耦合的输出电流能力。

公开(公告)号：US5872044A

公开(公告)日：1999-02-16

申请号：US733368

申请日：1996-10-17

申请人： Donald Frank Hemmenway ,  Lawrence George Pearce

发明人： Donald Frank Hemmenway ,  Lawrence George Pearce

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/7624 ,  H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286

摘要： Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCOS layer 25, is grown. The trenches 72 are also filled after a final deep diffusion, i.e. a diffusion in excess of one micron.

摘要翻译： 沟槽72在制造过程的后期形成在衬底17中。 为了避免在衬底单晶晶格中引起缺陷的沟槽侧壁应力，在生长最终厚的热氧化物层（例如LOCOS层25）之后填充沟槽。 沟槽72也在最终深度扩散之后填充，即扩散超过1微米。

公开(公告)号：US5777362A

公开(公告)日：1998-07-07

申请号：US474559

申请日：1995-06-07

申请人： Lawrence George Pearce

发明人： Lawrence George Pearce

IPC分类号： H01L27/06 ,  H01L29/06 ,  H01L29/10 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L29/76 ,  H01L27/01

CPC分类号： H01L29/41741 ,  H01L27/0623 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7809 ,  H01L29/456

摘要： A QVDMOS array 10 has QVDMOS devices with a silicide contact 42 to source 35 and body tie 36. The body tie 36 is enclosed by the source at the surface and extends beneath but not beyond the annular source 35. The QVDMOS is formed during a number of process steps that simultaneously form regions in NMOS, PMOS and bipolar devices.

摘要翻译： QVDMOS阵列10具有QVDMOS器件，其具有硅化物接触42至源极35和主体接头36.主体连接36由源封装在表面处并在下方但不超过环形源35。QVDMOS形成在数字 在NMOS，PMOS和双极器件中同时形成区域的工艺步骤。

公开(公告)号：US5689129A

公开(公告)日：1997-11-18

申请号：US483691

申请日：1995-06-07

申请人： Lawrence George Pearce

发明人： Lawrence George Pearce

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/45 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L29/4238 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/456

摘要： A power MOS switch (40) is an array of MOS devices that includes alternating drain columns and source columns. Each drain column includes a plurality of separate drain regions (300) that are closely spaced one from another, and each source column includes a continuous narrow elongated source distribution region (302) that extends the length of the column. A plurality of narrow source distribution branch regions (302) are connected to the elongated region and extend transversely from the elongated region at least partially between each separate drain region in each drain column adjacent to the source column. A gate region (303) separates the drain regions in each column from the adjacent source distribution regions.

摘要翻译： 功率MOS开关（40）是包括交替漏极列和源极列的MOS器件阵列。 每个漏极列包括彼此紧密间隔的多个分离的漏极区域（300），并且每个源极柱包括延伸柱的长度的连续窄的细长源极分布区域（302）。 多个窄源分布支路区域连接到细长区域，并且至少部分地在细长区域中横向地延伸到与源极柱相邻的每个漏极列中的每个分开的漏极区域之间。 栅极区域（303）将各列中的漏极区域与相邻的源极分布区域分离。

公开(公告)号：US07141941B2

公开(公告)日：2006-11-28

申请号：US10968480

申请日：2004-10-19

申请人： Robert L. Lyle, Jr. ,  Lawrence George Pearce

发明人： Robert L. Lyle, Jr. ,  Lawrence George Pearce

IPC分类号： H05B37/00 ,  H05B39/00 ,  H05B41/00 ,  H05B37/02 ,  H05B39/04 ,  H05B41/36 ,  G05F1/00

CPC分类号： H05B41/2824

摘要： In order to minimize switching-induced electromagnetic interference in a power supply switching circuit of the type used to control the AC power for multiple high voltage devices, such as cold cathode fluorescent lamps employed for backlighting a large scale liquid crystal display, the gating signals that are used to switch lamp-driving inverter circuits ON and OFF are staggered, or slightly offset in time, so that no two switching devices will be switched at the same time. By slightly offset in time is meant that the time differential between any pair of switching signals is relatively small compared to the period of the switching signal frequency. This has the effect of spreading out and thereby diminishing the magnitude of the spectral content of both capacitively and inductively coupled transients that are produced at switching times of the inverter circuits.

摘要翻译： 为了最小化用于控制多个高压装置（例如用于背光大规模液晶显示器的冷阴极荧光灯）的AC电源的电源开关电路中的开关感应电磁干扰，门控信号 用于开关灯驱动逆变器电路的ON和OFF交错，或稍微偏移时间，因此不会同时切换两个开关装置。 通过稍微偏移的时间是指任何一对开关信号之间的时间差与切换信号频率的周期相比相对较小。 这具有扩展并因此减小在逆变器电路的开关时间产生的电容和电感耦合瞬变的频谱含量的大小。

公开(公告)号：US5920108A

公开(公告)日：1999-07-06

申请号：US745104

申请日：1996-11-07

申请人： Donald Frank Hemmenway ,  Lawrence George Pearce

发明人： Donald Frank Hemmenway ,  Lawrence George Pearce

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L21/762 ,  H01L21/763 ,  H01L29/73 ,  H01L29/78 ,  H01L29/02

CPC分类号： H01L29/7824 ,  H01L21/76202 ,  H01L21/76264 ,  H01L21/763 ,  H01L29/66265 ,  H01L29/66772 ,  H01L29/7317 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286

摘要： Trenches 72 are formed in substrate 17 late in the fabrication process. In order to avoid trench sidewall stresses that cause defects in the substrate monocrystalline lattice, the trenches are filled after a final thick thermal oxide layer, such as a LOCOS layer 25, is grown. The trenches 72 are also filled after a final deep diffusion, i.e. a diffusion in excess of one micron.

摘要翻译： 沟槽72在制造过程的后期形成在衬底17中。 为了避免在衬底单晶晶格中引起缺陷的沟槽侧壁应力，在生长最终厚的热氧化物层（例如LOCOS层25）之后，填充沟槽。 沟槽72也在最终深度扩散之后填充，即扩散超过1微米。

公开(公告)号：US07700977B2

公开(公告)日：2010-04-20

申请号：US12037569

申请日：2008-02-26

申请人： Michael David Church ,  Alexander Kalnitsky ,  Lawrence George Pearce ,  Michael Ray Jayne ,  Thomas Andrew Jochum

发明人： Michael David Church ,  Alexander Kalnitsky ,  Lawrence George Pearce ,  Michael Ray Jayne ,  Thomas Andrew Jochum

IPC分类号： H01L23/62

CPC分类号： H01L27/0629 ,  H01L27/0255 ,  H01L27/0814

摘要： An integrated circuit includes a first and second diode connected in parallel. The first diode has a first breakdown voltage and has first P type region and first N type region adjacent to each other at the surface of the substrate of a substrate to form a lateral diode. The second diode has a second breakdown voltage less than the first breakdown voltage and has a second P type region and second N type region lateral adjacent to each other in the substrate to form a lateral diode below the surface The first and second N type regions overlap and the first and second P type region being electrically connected whereby the first and second diodes are in parallel.

摘要翻译： 集成电路包括并联连接的第一和第二二极管。 第一二极管具有第一击穿电压，并且在衬底的衬底的表面处具有彼此相邻的第一P型区域和第一N型区域，以形成横向二极管。 第二二极管具有小于第一击穿电压的第二击穿电压，并且在衬底中具有彼此相邻的第二P型区域和第二N型区域，以在表面下方形成横向二极管。第一和第二N型区域重叠 并且第一和第二P型区域电连接，由此第一和第二二极管是并联的。

公开(公告)号：US06906536B2

公开(公告)日：2005-06-14

申请号：US10720794

申请日：2003-11-24

申请人： Lawrence George Pearce ,  William David Bartlett

发明人： Lawrence George Pearce ,  William David Bartlett

IPC分类号： G01R31/40 ,  H02M3/158 ,  G01R27/08 ,  G05F1/565

CPC分类号： H02M3/1588 ,  G01R31/40 ,  H02M2001/0009 ,  Y02B70/1466

摘要： An arrangement for measuring current through a phase section of a buck mode DC-DC converter includes an auxiliary integrated circuit containing an auxiliary power MOSFET and a pilot MOSFET coupled in parallel with a current path through a high side MOSFET of a half-bridge of the converter. The pilot MOSFET has a current path coupled to a current measurement terminal. The MOSFETs of the auxiliary circuit are time division multiplexed with the high side MOSFET, whereby a determination of current through the auxiliary high side MOSFET is based upon current through the pilot device and the geometric ratio of the size of the pilot device to that of the high side auxiliary MOSFET. The high side MOSFET is activated for a large number of switching cycles relative to the pilot circuitry, but the pilot circuitry is activated sufficiently often to derive a relatively accurate measure of current flow.

摘要翻译： 用于测量通过降压模式DC-DC转换器的相位部分的电流的装置包括辅助集成电路，其包含辅助功率MOSFET和引导MOSFET，所述辅助功率MOSFET和引导MOSFET与通过半桥的高侧MOSFET的电流路径并联耦合 转换器。 导频MOSFET具有耦合到电流测量端子的电流路径。 辅助电路的MOSFET与高侧MOSFET进行时分多路复用，由此，通过辅助高侧MOSFET的电流的确定是基于通过导频装置的电流，以及导频装置的尺寸与 高边辅助MOSFET。 高边MOSFET相对于导频电路被激活大量的开关周期，但导频电路被充分激活，以导出电流的相对精确的测量。