公开(公告)号：US20050204228A1

公开(公告)日：2005-09-15

申请号：US11103783

申请日：2005-04-11

申请人： Lee Whetsel ,  Joel Graber

发明人： Lee Whetsel ,  Joel Graber

IPC分类号： G01R31/317 ,  G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318544 ,  G01R31/31721 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318547 ,  G01R31/318575 ,  G01R31/31858 ,  G01R31/318586

摘要： Scan and Scan-BIST architectures are commonly used to test digital circuitry in integrated circuits. The present invention improves upon low power Scan and Scan-BIST methods. The improvement allows the low power Scan and Scan-BIST architectures to achieve a delay test capability equally as effective as the delay test capabilities used in conventional scan and Scan-BIST architectures.

摘要翻译： 扫描和扫描BIST架构通常用于测试集成电路中的数字电路。 本发明改进了低功率扫描和扫描BIST方法。 该改进允许低功耗扫描和扫描BIST架构实现与传统扫描和Scan-BIST架构中使用的延迟测试功能一样有效的延迟测试功能。

公开(公告)号：US20050213411A1

公开(公告)日：2005-09-29

申请号：US11121387

申请日：2005-05-03

申请人： Manjeri Krishnan ,  Bryan Sheffield ,  Joel Graber ,  Duy-Loan Le ,  Sanjive Agarwala

发明人： Manjeri Krishnan ,  Bryan Sheffield ,  Joel Graber ,  Duy-Loan Le ,  Sanjive Agarwala

IPC分类号： G11C29/50 ,  G11C5/00

CPC分类号： G11C29/027 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012

摘要： Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.

公开(公告)号：US20050024960A1

公开(公告)日：2005-02-03

申请号：US10630963

申请日：2003-07-30

申请人： Manjeri Krishnan ,  Bryan Sheffield ,  Joel Graber ,  Duy-Loan Le ,  Sanjive Agarwala

发明人： Manjeri Krishnan ,  Bryan Sheffield ,  Joel Graber ,  Duy-Loan Le ,  Sanjive Agarwala

IPC分类号： G11C29/50 ,  G11C7/00

CPC分类号： G11C29/027 ,  G11C29/028 ,  G11C29/50 ,  G11C29/50012

摘要： Electrical fuses (eFuses) are applied to the task of memory performance adjustment to improve upon earlier fuse techniques by not requiring an additional processing step and expensive equipment. Standard electrical fuse (eFuse) hardware chains provide a soft test feature wherein the effect of memory slow-down can be tested prior to actually programming the fuses. Electrical fuses thus provide a very efficient non-volatile method to match the logic-memory interface through memory trimming, drastically cutting costs and cycle times involved.

公开(公告)号：US20050172180A1

公开(公告)日：2005-08-04

申请号：US11003206

申请日：2004-12-03

申请人： Raguram Damodaran ,  Timothy Anderson ,  Sanjive Agarwala ,  Joel Graber

发明人： Raguram Damodaran ,  Timothy Anderson ,  Sanjive Agarwala ,  Joel Graber

IPC分类号： G11C29/00 ,  G11C29/16

CPC分类号： G11C29/16

摘要： The pBIST solution to memory testing is a balanced hardware-software oriented solution. pBIST hardware provides access to all memories and other such logic (e.g. register files) in pipelined logic allowing back-to-back accesses. The approach then gives the user access to this logic through CPU-like logic in which the programmer can code any algorithm to target any memory testing technique required. Because hardware inside the chip is used at-speed, the full device speed capabilities are available. CPU-like hardware can be programmed and algorithms can be developed and executed after tape-out and while testing on devices in chip form is in process.

摘要翻译： 内存测试的pBIST解决方案是一个平衡的面向硬件的软件解决方案。 pBIST硬件提供对允许背靠背访问的流水线逻辑中的所有存储器和其他这样的逻辑（例如寄存器文件）的访问。 该方法然后让用户通过类似CPU的逻辑访问该逻辑，其中程序员可以对任何算法进行编码，以定位所需的任何内存测试技术。 由于芯片内部的硬件速度被使用，因此可以提供全部设备速度功能。 类似CPU的硬件可以进行编程，并且可以在磁带输出之后开发和执行算法，同时在芯片形式的器件上进行测试。