Power integrity circuits with EMI benefits
    1.
    发明授权
    Power integrity circuits with EMI benefits 有权
    具有EMI优势的电源完整性电路

    公开(公告)号:US08514549B2

    公开(公告)日:2013-08-20

    申请号:US13048738

    申请日:2011-03-15

    IPC分类号: H01G4/228

    摘要: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

    摘要翻译: 公开了一种用于连接电子设备和电路板的稳定功率,低电磁干扰(EMI)装置和方法。 该装置包括电容器,其包括主体构件,一组电源端子和连接到主体构件的顶部的一组接地端子。 电源端子组和接地端子组彼此交替。 作为该结构的结果,实现了PCB侧的高电感。 电容器还包括连接到本体构件的底部并且包括主体构件内的金属平面的一组端子。 金属平面定位成将一组电源端子或一组接地端子电连接到该组端子。

    POWER INTEGRITY CIRCUITS WITH EMI BENEFITS
    2.
    发明申请
    POWER INTEGRITY CIRCUITS WITH EMI BENEFITS 有权
    具有EMI优势的电源整合电路

    公开(公告)号:US20110164392A1

    公开(公告)日:2011-07-07

    申请号:US13048738

    申请日:2011-03-15

    摘要: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

    摘要翻译: 公开了一种用于连接电子设备和电路板的稳定功率,低电磁干扰(EMI)装置和方法。 该装置包括电容器,其包括主体构件,一组电源端子和连接到主体构件的顶部的一组接地端子。 电源端子组和接地端子组彼此交替。 作为该结构的结果,实现了PCB侧的高电感。 电容器还包括连接到本体构件的底部并且包括主体构件内的金属平面的一组端子。 金属平面定位成将一组电源端子或一组接地端子电连接到该组端子。

    Power integrity circuits with EMI benefits
    3.
    发明授权
    Power integrity circuits with EMI benefits 有权
    具有EMI优势的电源完整性电路

    公开(公告)号:US07969712B2

    公开(公告)日:2011-06-28

    申请号:US11737484

    申请日:2007-04-19

    IPC分类号: H01G4/228

    摘要: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

    摘要翻译: 公开了一种用于连接电子设备和电路板的稳定功率,低电磁干扰(EMI)装置和方法。 该装置包括电容器,其包括主体构件,一组电源端子和连接到主体构件的顶部的一组接地端子。 电源端子组和接地端子组彼此交替。 作为该结构的结果,实现了PCB侧的高电感。 电容器还包括连接到本体构件的底部并且包括主体构件内的金属平面的一组端子。 金属平面定位成将一组电源端子或一组接地端子电连接到该组端子。

    POWER INTEGRITY CIRCUITS WITH EMI BENEFITS
    4.
    发明申请
    POWER INTEGRITY CIRCUITS WITH EMI BENEFITS 有权
    具有EMI优势的电源整合电路

    公开(公告)号:US20080259521A1

    公开(公告)日:2008-10-23

    申请号:US11737484

    申请日:2007-04-19

    IPC分类号: H01G4/00

    摘要: A stable power, low electromagnetic interference (EMI) apparatus and method for connecting electronic devices and circuit boards is disclosed. The apparatus involves a capacitor which includes a body member, a set of power terminals and a set of ground terminals connected to the top of the body member. The set of power terminals and the set of ground terminals alternate one with another. As a result of this configuration, a high inductance on the PCB side is achieved. The capacitor further includes a set of terminals connected to the bottom of the body member and includes metal planes within the body member. The metal planes are positioned to electrically connect either the set of power terminals or the set of ground terminals to the set of terminals.

    摘要翻译: 公开了一种用于连接电子设备和电路板的稳定功率,低电磁干扰(EMI)装置和方法。 该装置包括电容器,其包括主体构件,一组电源端子和连接到主体构件的顶部的一组接地端子。 电源端子组和接地端子组彼此交替。 作为该结构的结果,实现了PCB侧的高电感。 电容器还包括连接到本体构件的底部并且包括主体构件内的金属平面的一组端子。 金属平面定位成将一组电源端子或一组接地端子电连接到该组端子。

    Conductor arrangement for reduced noise differential signalling
    5.
    发明申请
    Conductor arrangement for reduced noise differential signalling 有权
    用于降低噪声差分信号的导体布置

    公开(公告)号:US20050210162A1

    公开(公告)日:2005-09-22

    申请号:US10804447

    申请日:2004-03-19

    申请人: Leesa Noujeim

    发明人: Leesa Noujeim

    IPC分类号: G01R19/00 G06F17/50

    CPC分类号: G06F17/5068

    摘要: A method for analyzing input output (I/O) pin arrangements to determine the effect of differential pair and power and ground pin placement on signal quality which includes constructing an array of pins, arranging a plurality of differential pairs within the array of pins to provide a pin arrangement, exciting each of the differential pairs within the pin arrangement, monitoring coupled noise on other differential pairs within the pin arrangement, and analyzing the pin arrangement based upon the monitoring.

    摘要翻译: 一种用于分析输入输出(I / O)引脚布置以确定差分对和电源和接地引脚布置对信号质量的影响的方法,其包括构造引脚阵列,在引脚阵列内布置多个差分对以提供 引脚布置,激励引脚布置内的每个差分对,监测引脚布置内的其它差分对上的耦合噪声,以及基于监视来分析引脚布置。

    Method to test power distribution system
    6.
    发明授权
    Method to test power distribution system 有权
    配电系统的测试方法

    公开(公告)号:US06925616B2

    公开(公告)日:2005-08-02

    申请号:US10265035

    申请日:2002-10-04

    CPC分类号: G01R31/31721

    摘要: A method for testing a core power distribution system for an integrated circuit chip which includes arranging a plurality of experiments for an integrated circuit chip, performing the plurality of experiments for the integrated circuit chip over a range of frequencies over a range of power distribution system impedances, generating a schmoo diagram for each of the plurality of experiments, and analyzing the schmoo diagrams to determine whether the core power distribution system functions is acceptable at a particular frequency.

    摘要翻译: 一种用于测试用于集成电路芯片的核心配电系统的方法,其包括为集成电路芯片布置多个实验,在一系列配电系统阻抗的一定范围内对集成电路芯片执行多个实验 ,为所述多个实验中的每一个生成schmoo图,以及分析所述schmoo图以确定所述核心配电系统功能是否在特定频率下是可接受的。