Area-efficient gated diode structure and method of forming same
    1.
    发明申请
    Area-efficient gated diode structure and method of forming same 有权
    区域效能门控二极管结构及其形成方法

    公开(公告)号:US20070164359A1

    公开(公告)日:2007-07-19

    申请号:US11334170

    申请日:2006-01-18

    IPC分类号: H01L27/12

    摘要: An area-efficient gated diode includes a semiconductor layer of a first conductivity type, an active region of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer, and at least one trench electrode extending substantially vertically through the active region and at least partially into the semiconductor layer. A first terminal of the gated diode is electrically connected to the trench electrode, and at least a second terminal is electrically connected to the active region. The gated diode is operative in one of at least a first mode and a second mode as a function of a voltage potential applied between the first and second terminals. The first mode is characterized by the creation of an inversion layer in the semiconductor layer substantially surrounding the trench electrode. The gated diode has a first capacitance in the first mode and a second capacitance in the second mode, the first capacitance being substantially greater than the second capacitance.

    摘要翻译: 区域有效的门控二极管包括第一导电类型的半导体层,形成在靠近半导体层的上表面的半导体层中的第二导电类型的有源区,以及至少一个沟槽电极,该沟槽电极基本垂直延伸穿过活性层 并且至少部分地进入半导体层。 门控二极管的第一端子电连接到沟槽电极,并且至少第二端子电连接到有源区域。 门控二极管作为施加在第一和第二端子之间的电压电位的函数的至少第一模式和第二模式中的一个工作。 第一模式的特征在于在基本上围绕沟槽电极的半导体层中产生反型层。 门控二极管具有第一模式中的第一电容和第二模式中的第二电容,第一电容基本上大于第二电容。

    DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION
    5.
    发明申请
    DOUBLE GATED TRANSISTOR AND METHOD OF FABRICATION 有权
    双栅极晶体管和制造方法

    公开(公告)号:US20070254438A1

    公开(公告)日:2007-11-01

    申请号:US11774663

    申请日:2007-07-09

    IPC分类号: H01L21/336

    摘要: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

    摘要翻译: 一种形成晶体管的方法。 提供半导体衬底。 图案化半导体衬底以提供第一本体边缘。 在第一身体边缘附近提供第一费米能级的第一门结构。 图案化半导体衬底以提供第二本体边缘。 半导体衬底的第一和第二主体边缘限定晶体管体。 在第二身体边缘附近设置第二费米能级的第二门结构。 在整个晶体管本体中形成基本均匀的掺杂剂浓度密度。

    Methods of forming structure and spacer and related finfet
    7.
    发明申请
    Methods of forming structure and spacer and related finfet 审中-公开
    形成结构和间隔物及相关鳍的方法

    公开(公告)号:US20060154423A1

    公开(公告)日:2006-07-13

    申请号:US10538911

    申请日:2002-12-19

    IPC分类号: H01L21/336

    CPC分类号: H01L29/785 H01L29/66795

    摘要: Methods for forming a spacer (44) for a first structure (24, 124), such as a gate structure of a FinFET, and at most a portion of a second structure (14), such as a fin, without detrimentally altering the second structure. The methods generate a first structure (24) having a top portion (30, 130) that overhangs an electrically conductive lower portion (32, 132) and a spacer (44) under the overhang (40, 140). The overhang (40, 140) may be removed after spacer processing. Relative to a FinFET, the overhang protects parts of the fin (14) such as regions adjacent and under the gate structure (24, 124), and allows for exposing sidewalls of the fin (14) to other processing such as selective silicon growth and implantation. As a result, the methods allow sizing of the fin (14) and construction of the gate structure (24, 124) and spacer without detrimentally altering (e.g., eroding by forming a spacer thereon) the fin (14) during spacer processing. A FinFET (100) including a gate structure (24, 124) and spacer (44) is also disclosed.

    摘要翻译: 用于形成用于第一结构(24,124)的间隔物(44)的方法,诸如FinFET的栅极结构,以及至少一部分第二结构(14)的一部分,例如翅片,而不会有害地改变第二结构 结构体。 该方法产生第一结构(24),该第一结构(24)具有突出在导电下部(32,132)之下的顶部(30,130)和在突出部(40,140)下方的间隔物(44)。 间隔物处理后,可以移除悬垂物(40,140)。 相对于FinFET,突出端保护翅片(14)的部分,例如在栅极结构(24,124)附近和下方的区域,并且允许将鳍片(14)的侧壁暴露于诸如选择性硅生长的其它处理,以及 植入。 结果,这些方法允许翅片(14)的尺寸和栅极结构(24,124)和间隔物的结构,而不会在间隔物处理期间有害地改变(例如,通过在其上形成隔离物的侵蚀)翅片(14)。 还公开了包括栅极结构(24,124)和间隔物(44)的FinFET(100)。

    Computer-aided online card games using multiple online player preferences
    9.
    发明授权
    Computer-aided online card games using multiple online player preferences 有权
    使用多种在线播放器偏好的计算机辅助在线纸牌游戏

    公开(公告)号:US09144739B2

    公开(公告)日:2015-09-29

    申请号:US13544635

    申请日:2012-07-09

    IPC分类号: G07F17/32 A63F13/30

    摘要: A method, computer system, and computer program product to assign player-entries in an online card game. The method commences by receiving preference parameters corresponding to a player, then receiving a player command corresponding to the player to fold out of a current hand of a particular game. For alacrity of play and for supporting a large number of concurrently open tables for an online player to play a large number of games, the method proceeds to identify an open table that satisfies player preference parameters. The preferred game and/or the player's preferred seating arrangement can be determined by using a second preference parameter. The method can respond to a fold-out command by the player and can open a new table on the basis of the player's preference parameters.

    摘要翻译: 一种方法,计算机系统和计算机程序产品,用于在在线纸牌游戏中分配玩家条目。 该方法通过接收与玩家相对应的偏好参数而开始,然后接收与玩家相对应的玩家命令以折叠特定游戏的当前手。 为了玩游戏的可行性,并且支持大量的在线玩家同时打开的桌子来玩大量的游戏,该方法继续识别满足玩家偏好参数的开放表。 可以通过使用第二偏好参数来确定首选游戏和/或玩家的优选座位布置。 该方法可以响应播放器的折叠命令,并且可以基于玩家的偏好参数来打开一个新的表。

    Formation of capacitor having a Fin structure

    公开(公告)号:US20060038216A1

    公开(公告)日:2006-02-23

    申请号:US11216862

    申请日:2005-08-31

    IPC分类号: H01L29/94

    摘要: Device designs and methods are described for incorporating capacitors commonly used in planar CMOS technology into a FinFET based technology. A capacitor includes at least one single-crystal Fin structure having a top surface and a first side surface opposite a second side surface. Adjacent the top surface of the at least one Fin structure is at least one insulator structure. Adjacent the at least one insulator structure and over a portion of the at least one Fin structure is at least one conductor structure. Decoupling capacitors may be formed at the circuit device level using simple design changes within the same integration method, thereby allowing any number, combination, and/or type of decoupling capacitors to be fabricated easily along with other devices on the same substrate to provide effective decoupling capacitance in an area-efficient manner with superior high-frequency response.