公开(公告)号：US20200098878A1

公开(公告)日：2020-03-26

申请号：US16139252

申请日：2018-09-24

申请人： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

发明人： Leonard P. GULER ,  Biswajeet GUHA ,  Tahir GHANI ,  Swaminathan SIVAKUMAR

IPC分类号： H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8234 ,  H01L27/088

摘要： Self-aligned gate endcap architectures with gate-all-around devices having epitaxial source or drain structures are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. A gate endcap isolation structure is between the first and second gate stacks, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires and have an uppermost surface below an uppermost surface of the gate endcap isolation structure. Second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires and have an uppermost surface below the uppermost surface of the gate endcap isolation structure.

公开(公告)号：US20190393352A1

公开(公告)日：2019-12-26

申请号：US16017966

申请日：2018-06-25

申请人： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

发明人： Biswajeet GUHA ,  William HSU ,  Leonard P. GULER ,  Dax M. CRUM ,  Tahir GHANI

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02 ,  H01L21/8234 ,  H01L23/522

摘要： Self-aligned gate endcap (SAGE) architectures with gate-all-around devices, and methods of fabricating self-aligned gate endcap (SAGE) architectures with gate-all-around devices, are described. In an example, an integrated circuit structure includes a semiconductor fin above a substrate and having a length in a first direction. A nanowire is over the semiconductor fin. A gate structure is over the nanowire and the semiconductor fin, the gate structure having a first end opposite a second end in a second direction, orthogonal to the first direction. A pair of gate endcap isolation structures is included, where a first of the pair of gate endcap isolation structures is spaced equally from a first side of the semiconductor fin as a second of the pair of gate endcap isolation structures is spaced from a second side of the semiconductor fin.

公开(公告)号：US20230207696A1

公开(公告)日：2023-06-29

申请号：US17561518

申请日：2021-12-23

申请人： Mohammad HASAN ,  Wonil CHUNG ,  Biswajeet GUHA ,  Saptarshi MANDAL ,  Pratik PATEL ,  Tahir GHANI ,  Stephen M. CEA ,  Anand S. MURTHY

发明人： Mohammad HASAN ,  Wonil CHUNG ,  Biswajeet GUHA ,  Saptarshi MANDAL ,  Pratik PATEL ,  Tahir GHANI ,  Stephen M. CEA ,  Anand S. MURTHY

IPC分类号： H01L29/78 ,  H01L29/423

CPC分类号： H01L29/7843 ,  H01L29/785 ,  H01L29/42392

摘要： Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to integrated circuits utilizing gate plugs to induce compressive channel strain. Other embodiments may be described or claimed.