公开(公告)号：US07132353B1

公开(公告)日：2006-11-07

申请号：US11195398

申请日：2005-08-02

申请人： Li-Qun Xia ,  Mei-Yee Shek ,  Troy Kim ,  Vladamir Zubkov ,  Ritwik Bhatia

发明人： Li-Qun Xia ,  Mei-Yee Shek ,  Troy Kim ,  Vladamir Zubkov ,  Ritwik Bhatia

IPC分类号： H01L21/3205

CPC分类号： H01L29/6656 ,  H01L21/3145 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a sidewall spacer on a gate electrode is described. The method includes generating a first plasma from a silicon containing precursor and oxide precursor, and forming a silicon oxy-nitride layer on the sidewall of the gate electrode. The method also includes generating a second plasma from the silicon containing precursor and a nitrogen precursor, and forming a nitride layer on the silicon oxy-nitride layer. The silicon containing precursor can flow continuously between the generation of the first and the second plasmas. Also, a method of forming a sidewall spacer on the side of a gate electrode on a substrate. The method includes forming an oxy-nitride layer on the sidewall, and forming a nitride layer on the oxy-nitride layer, where the substrate wafer is not exposed to air between the formation of the layers.

摘要翻译： 描述了在栅极上形成侧壁间隔物的方法。 该方法包括从含硅前体和氧化物前体产生第一等离子体，并在栅电极的侧壁上形成氮氧化硅层。 该方法还包括从含硅前体和氮前体产生第二等离子体，并在氮氧化硅层上形成氮化物层。 含硅前体可以在第一和第二等离子体的产生之间连续流动。 另外，在基板上的栅电极侧形成侧墙的方法。 该方法包括在侧壁上形成氮氧化物层，并且在氧化氮化物层上形成氮化物层，其中衬底晶片在层的形成之间不暴露于空气。

公开(公告)号：US20090137132A1

公开(公告)日：2009-05-28

申请号：US12365669

申请日：2009-02-04

申请人： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

发明人： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

IPC分类号： H01L21/31

CPC分类号： H01L21/0332 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/76825 ,  H01L21/76829

摘要： Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.

摘要翻译： 提供了形成氮化硅硬掩模的方法。 氮化硅硬掩模包括碳掺杂的氮化硅层和未掺杂的氮化硅层。 提供了在RF功率存在下由包含碳源化合物，硅源化合物和氮源的混合物沉积的碳掺杂氮化硅层。 还提供了UV后处理氮化硅层以提供氮化硅硬掩模的方法。 碳掺杂的氮化硅层和UV后处理的氮化硅层对于硬掩模层具有期望的湿蚀刻速率和干蚀刻速率。

公开(公告)号：US07501355B2

公开(公告)日：2009-03-10

申请号：US11478273

申请日：2006-06-29

申请人： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

发明人： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/0332 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/76825 ,  H01L21/76829

摘要： Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.

摘要翻译： 提供了形成氮化硅硬掩模的方法。 氮化硅硬掩模包括碳掺杂的氮化硅层和未掺杂的氮化硅层。 提供了在RF功率存在下由包含碳源化合物，硅源化合物和氮源的混合物沉积的碳掺杂氮化硅层。 还提供了UV后处理氮化硅层以提供氮化硅硬掩模的方法。 碳掺杂的氮化硅层和UV后处理的氮化硅层对于硬掩模层具有期望的湿蚀刻速率和干蚀刻速率。

公开(公告)号：US20080014761A1

公开(公告)日：2008-01-17

申请号：US11478273

申请日：2006-06-29

申请人： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

发明人： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/0332 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/76825 ,  H01L21/76829

摘要： Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.

摘要翻译： 提供了形成氮化硅硬掩模的方法。 氮化硅硬掩模包括碳掺杂的氮化硅层和未掺杂的氮化硅层。 提供了在RF功率存在下从包含碳源化合物，硅源化合物和氮源的混合物沉积的碳掺杂氮化硅层。 还提供了UV后处理氮化硅层以提供氮化硅硬掩模的方法。 碳掺杂的氮化硅层和UV后处理的氮化硅层对于硬掩模层具有期望的湿蚀刻速率和干蚀刻速率。

公开(公告)号：US07951730B2

公开(公告)日：2011-05-31

申请号：US12365669

申请日：2009-02-04

申请人： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

发明人： Ritwik Bhatia ,  Li-Qun Xia ,  Chad Peterson ,  Hichem M'Saad

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/0332 ,  H01L21/3105 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/76825 ,  H01L21/76829

摘要： Methods for forming silicon nitride hard masks are provided. The silicon nitride hard masks include carbon-doped silicon nitride layers and undoped silicon nitride layers. Carbon-doped silicon nitride layers that are deposited from a mixture comprising a carbon source compound, a silicon source compound, and a nitrogen source in the presence of RF power are provided. Also provided are methods of UV post-treating silicon nitride layers to provide silicon nitride hard masks. The carbon-doped silicon nitride layers and UV post-treated silicon nitride layers have desirable wet etch rates and dry etch rates for hard mask layers.

摘要翻译： 提供了形成氮化硅硬掩模的方法。 氮化硅硬掩模包括碳掺杂的氮化硅层和未掺杂的氮化硅层。 提供了在RF功率存在下由包含碳源化合物，硅源化合物和氮源的混合物沉积的碳掺杂氮化硅层。 还提供了UV后处理氮化硅层以提供氮化硅硬掩模的方法。 碳掺杂的氮化硅层和UV后处理的氮化硅层对于硬掩模层具有期望的湿蚀刻速率和干蚀刻速率。

公开(公告)号：US07737052B2

公开(公告)日：2010-06-15

申请号：US12042873

申请日：2008-03-05

申请人： Ritwik Bhatia ,  Griselda Bonilla ,  Alfred Grill ,  Joshua L. Herman ,  Son Van Nguyen ,  E. Todd Ryan ,  Hosadurga Shobha

发明人： Ritwik Bhatia ,  Griselda Bonilla ,  Alfred Grill ,  Joshua L. Herman ,  Son Van Nguyen ,  E. Todd Ryan ,  Hosadurga Shobha

IPC分类号： H01L21/31 ,  H01L21/469 ,  H01L23/58 ,  H01L23/48

CPC分类号： H01L21/76834 ,  H01L21/02348 ,  H01L21/76832

摘要： A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N bonds at the interface of a conductive material such as, for example, Cu. The dielectric cap exhibits a high compressive stress and high modulus and is still remain compressive stress under post-deposition curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

摘要翻译： 公开了包含相同方法和相关方法的电介质盖，互连结构。 本发明的电介质盖包括多层介电材料堆叠，其中叠层的至少一层在后沉积固化处理期间具有良好的抗氧化性，Cu扩散和/或显着更高的机械稳定性，并且包括Si-N键在 导电材料，例如Cu。 电介质盖表现出高压缩应力和高模量，并且在后沉积固化处理时仍然保持压应力，例如：铜低k后端（BEOL）纳米电子器件，导致较少的膜和器件 开裂和可靠性提高。

公开(公告)号：US20090224374A1

公开(公告)日：2009-09-10

申请号：US12042873

申请日：2008-03-05

申请人： Ritwik Bhatia ,  Griselda Bonilla ,  Alfred Grill ,  Joshua L. Herman ,  Son Van Nguyen ,  E. Todd Ryan ,  Hosadurga Shobha

发明人： Ritwik Bhatia ,  Griselda Bonilla ,  Alfred Grill ,  Joshua L. Herman ,  Son Van Nguyen ,  E. Todd Ryan ,  Hosadurga Shobha

IPC分类号： H01L23/538 ,  H01L23/58 ,  H01L21/31 ,  H01L21/768

CPC分类号： H01L21/76834 ,  H01L21/02348 ,  H01L21/76832

摘要： A dielectric cap, interconnect structure containing the same and related methods are disclosed. The inventive dielectric cap includes a multilayered dielectric material stack wherein at least one layer of the stack has good oxidation resistance, Cu diffusion and/or substantially higher mechanical stability during a post-deposition curing treatment, and including Si—N bonds at the interface of a conductive material such as, for example, Cu. The dielectric cap exhibits a high compressive stress and high modulus and is still remain compressive stress under post-deposition curing treatments for, for example: copper low k back-end-of-line (BEOL) nanoelectronic devices, leading to less film and device cracking and improved reliability.

摘要翻译： 公开了包含相同方法和相关方法的电介质盖，互连结构。 本发明的电介质盖包括多层介电材料堆叠，其中叠层的至少一层在后沉积固化处理期间具有良好的抗氧化性，Cu扩散和/或显着更高的机械稳定性，并且包括Si-N键在 导电材料，例如Cu。 电介质盖表现出高压缩应力和高模量，并且在后沉积固化处理时仍然保持压应力，例如：铜低k后端（BEOL）纳米电子器件，导致较少的膜和器件 开裂和可靠性提高。