公开(公告)号：US07132353B1

公开(公告)日：2006-11-07

申请号：US11195398

申请日：2005-08-02

申请人： Li-Qun Xia ,  Mei-Yee Shek ,  Troy Kim ,  Vladamir Zubkov ,  Ritwik Bhatia

发明人： Li-Qun Xia ,  Mei-Yee Shek ,  Troy Kim ,  Vladamir Zubkov ,  Ritwik Bhatia

IPC分类号： H01L21/3205

CPC分类号： H01L29/6656 ,  H01L21/3145 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A method of forming a sidewall spacer on a gate electrode is described. The method includes generating a first plasma from a silicon containing precursor and oxide precursor, and forming a silicon oxy-nitride layer on the sidewall of the gate electrode. The method also includes generating a second plasma from the silicon containing precursor and a nitrogen precursor, and forming a nitride layer on the silicon oxy-nitride layer. The silicon containing precursor can flow continuously between the generation of the first and the second plasmas. Also, a method of forming a sidewall spacer on the side of a gate electrode on a substrate. The method includes forming an oxy-nitride layer on the sidewall, and forming a nitride layer on the oxy-nitride layer, where the substrate wafer is not exposed to air between the formation of the layers.

摘要翻译： 描述了在栅极上形成侧壁间隔物的方法。 该方法包括从含硅前体和氧化物前体产生第一等离子体，并在栅电极的侧壁上形成氮氧化硅层。 该方法还包括从含硅前体和氮前体产生第二等离子体，并在氮氧化硅层上形成氮化物层。 含硅前体可以在第一和第二等离子体的产生之间连续流动。 另外，在基板上的栅电极侧形成侧墙的方法。 该方法包括在侧壁上形成氮氧化物层，并且在氧化氮化物层上形成氮化物层，其中衬底晶片在层的形成之间不暴露于空气。

公开(公告)号：US20130333923A1

公开(公告)日：2013-12-19

申请号：US13495545

申请日：2012-06-13

申请人： Mihaela Balseanu ,  Stephan A. Cohen ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Son V. Nguyen ,  Mei-Yee Shek ,  Hosadurga Shobha ,  Li-Qun Xia

发明人： Mihaela Balseanu ,  Stephan A. Cohen ,  Alfred Grill ,  Thomas J. Haigh, JR. ,  Son V. Nguyen ,  Mei-Yee Shek ,  Hosadurga Shobha ,  Li-Qun Xia

IPC分类号： C23C16/34 ,  H05K1/02

CPC分类号： C23C16/345 ,  C23C16/56 ,  H01L21/4803 ,  H05K1/0298 ,  Y10T428/24975

摘要： A layer of silicon nitride having a thickness from 0.5 nanometers to 2.4 nanometers is deposited on a substrate. A plasma nitridation process is carried out on the layer. These steps are repeated for a plurality of additional layers of silicon nitride, until a predetermined thickness is attained. Such steps can be used to provide a multilayer silicon nitride dielectric formed on a substrate having an upper surface of dielectric material with Cu and other conductors embedded within, and a plurality of steps. The multilayer silicon nitride dielectric has a plurality of individual layers each having a thickness from 0.5 nanometers to 2.4 nanometers, and the multilayer silicon nitride dielectric conformally covers the steps of the substrate with a conformality of at least seventy percent. A multilayer silicon nitride dielectric, and a multilevel back end of line interconnect wiring structure using same, are also provided.

摘要翻译： 将厚度为0.5纳米至2.4纳米的氮化硅层沉积在基底上。 在层上进行等离子体氮化处理。 对于多个附加氮化硅层重复这些步骤，直到达到预定厚度。 可以使用这样的步骤来提供形成在具有介电材料的上表面的衬底上的多层氮化硅电介质，其中Cu和其它导体嵌入其中并且多个步骤。 多层氮化硅电介质具有各自具有0.5纳米至2.4纳米厚度的多个单独层，多层氮化硅电介质保形地覆盖具有至少百分之七十的保形度的基底的步骤。 还提供了多层氮化硅电介质，以及使用该多层氮化硅电介质的多层后端的布线结构。

公开(公告)号：US07923386B2

公开(公告)日：2011-04-12

申请号：US12560941

申请日：2009-09-16

申请人： Mihaela Balseanu ,  Mei-yee Shek ,  Li-Qun Xia ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Mei-yee Shek ,  Li-Qun Xia ,  Hichem M'Saad

IPC分类号： H01L21/31

CPC分类号： H01L21/76834 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31612 ,  H01L21/31633 ,  H01L21/76829 ,  H01L21/76831

摘要： A method of forming a layer on a substrate in a chamber, wherein the substrate has at least one formed feature across its surface, is provided. The method includes exposing the substrate to a silicon-containing precursor in the presence of a plasma to deposit a layer, treating the deposited layer with a plasma, and repeating the exposing and treating until a desired thickness of the layer is obtained. The plasma may be generated from an oxygen-containing gas.

摘要翻译： 提供了一种在室中的衬底上形成层的方法，其中衬底在其表面上具有至少一个形成的特征。 该方法包括在存在等离子体的情况下将衬底暴露于含硅前体以沉积一层，用等离子体处理沉积层，并重复曝光和处理，直到获得所需层厚。 等离子体可以由含氧气体产生。

公开(公告)号：US20050042889A1

公开(公告)日：2005-02-24

申请号：US10888110

申请日：2004-07-09

申请人： Albert Lee ,  Annamalai Lakshmanan ,  Bok Kim ,  Li-Qun Xia ,  Mei-Yee Shek

发明人： Albert Lee ,  Annamalai Lakshmanan ,  Bok Kim ,  Li-Qun Xia ,  Mei-Yee Shek

IPC分类号： C23C16/30 ,  C23C16/40 ,  C23C16/56 ,  H01L21/311 ,  H01L21/312 ,  H01L21/316 ,  H01L21/768 ,  H01L21/31 ,  H01L21/336 ,  H01L21/469

CPC分类号： C23C16/30 ,  C23C16/401 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02167 ,  H01L21/022 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/02315 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/7681 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834

摘要： Methods and apparatus are provided for processing a substrate with a bilayer barrier layer. In one aspect, the invention provides a method for processing a substrate including depositing a nitrogen containing barrier layer on a substrate surface and then depositing a nitrogen free barrier layer thereon. The barrier layer may be deposited over dielectric materials, conductive materials, or both. The bilayer barrier layer may also be used as an etch stop, an anti-reflective coating, or a passivation layer.

摘要翻译： 提供了用于处理具有双层阻挡层的衬底的方法和装置。 一方面，本发明提供了一种处理衬底的方法，包括在衬底表面上沉积含氮阻挡层，然后在其上沉积无氮阻挡层。 阻挡层可以沉积在电介质材料，导电材料或两者上。 双层阻挡层也可以用作蚀刻停止层，抗反射涂层或钝化层。

公开(公告)号：US08481422B2

公开(公告)日：2013-07-09

申请号：US13455299

申请日：2012-04-25

申请人： Kelvin Chan ,  Khaled A. Elsheref ,  Alexandros T. Demos ,  Mei-Yee Shek ,  Lipan Li ,  Li-Qun Xia ,  Kang Sub Yim

发明人： Kelvin Chan ,  Khaled A. Elsheref ,  Alexandros T. Demos ,  Mei-Yee Shek ,  Lipan Li ,  Li-Qun Xia ,  Kang Sub Yim

IPC分类号： H01L21/4763

CPC分类号： H01L21/3141 ,  H01L21/02164 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/31116 ,  H01L21/31608 ,  H01L21/76814 ,  H01L21/76831

摘要： A method and apparatus for treating a substrate is provided. A porous dielectric layer is formed on the substrate. In some embodiments, the dielectric may be capped by a dense dielectric layer. The dielectric layers are patterned, and a dense dielectric layer deposited conformally over the substrate. The dense conformal dielectric layer seals the pores of the porous dielectric layer against contact with species that may infiltrate the pores. The portion of the dense conformal pore-sealing dielectric layer covering the field region and bottom portions of the pattern openings is removed by directional selective etch.

摘要翻译： 提供了一种处理基板的方法和装置。 在基板上形成多孔介电层。 在一些实施例中，电介质可以由致密的电介质层封盖。 对电介质层进行图案化，并且将致密的电介质层保形地沉积在衬底上。 密实的保形介电层密封多孔介电层的孔隙，防止与可能渗入孔隙的物质接触。 通过方向选择性蚀刻去除覆盖图案开口的场区域和底部的稠密共形孔隙电介质层的部分。

公开(公告)号：US08343881B2

公开(公告)日：2013-01-01

申请号：US12794713

申请日：2010-06-04

申请人： Yong-Won Lee ,  Vladimir Zubkov ,  Mei-Yee Shek ,  Li-Qun Xia ,  Prahallad Iyengar ,  Sanjeev Baluja ,  Scott A Hendrickson ,  Juan Carlos Rocha-Alvarez ,  Thomas Nowak ,  Derek R Witty

发明人： Yong-Won Lee ,  Vladimir Zubkov ,  Mei-Yee Shek ,  Li-Qun Xia ,  Prahallad Iyengar ,  Sanjeev Baluja ,  Scott A Hendrickson ,  Juan Carlos Rocha-Alvarez ,  Thomas Nowak ,  Derek R Witty

IPC分类号： H01L29/06 ,  H01L21/31 ,  C23C16/448

CPC分类号： H01L21/02271 ,  C23C16/402 ,  H01L21/02164 ,  H01L21/0332 ,  H01L21/76898

摘要： A silicon dioxide layer is deposited onto a substrate using a process gas comprising BDEAS and an oxygen-containing gas such as ozone. The silicon dioxide layer can be part of an etch-resistant stack that includes a resist layer. In another version, the silicon dioxide layer is deposited into through holes to form an oxide liner for through-silicon vias.

摘要翻译： 使用包含BDEAS和含氧气体如臭氧的工艺气体将二氧化硅层沉积到衬底上。 二氧化硅层可以是包括抗蚀剂层的抗蚀刻堆叠的一部分。 在另一个版本中，二氧化硅层被沉积到通孔中以形成用于通硅通孔的氧化物衬垫。

公开(公告)号：US20120196452A1

公开(公告)日：2012-08-02

申请号：US13365229

申请日：2012-02-02

申请人： Mihaela Balseanu ,  Michael S. Cox ,  Li-Qun Xia ,  Mei-Yee Shek ,  Jia Lee ,  Vladimir Zubkov ,  Tzu-Fang Huang ,  Rongping Wang ,  Isabelita Roflox ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Michael S. Cox ,  Li-Qun Xia ,  Mei-Yee Shek ,  Jia Lee ,  Vladimir Zubkov ,  Tzu-Fang Huang ,  Rongping Wang ,  Isabelita Roflox ,  Hichem M'Saad

IPC分类号： H01L21/318

CPC分类号： C23C16/345 ,  C23C16/45523 ,  C23C16/56 ,  H01L21/3141 ,  H01L21/3185 ,  H01L21/823412 ,  H01L21/82345 ,  H01L21/823807 ,  H01L21/823835

摘要： High tensile stress in a deposited layer, such as a silicon nitride layer, may be achieved utilizing one or more techniques employed either alone or in combination. In one embodiment, a silicon nitride film having high tensile stress may be formed by depositing the silicon nitride film in the presence of a porogen. The deposited silicon nitride film may be exposed to at least one treatment selected from a plasma or ultraviolet radiation to liberate the porogen. The silicon nitride film may be densified such that a pore resulting from liberation of the porogen is reduced in size, and Si—N bonds in the silicon nitride film are strained to impart a tensile stress in the silicon nitride film. In another embodiment, tensile stress in a silicon nitride film may be enhanced by depositing a silicon nitride film in the presence of a nitrogen-containing plasma at a temperature of less than about 400° C., and exposing the deposited silicon nitride film to ultraviolet radiation.

摘要翻译： 沉积层（例如氮化硅层）中的高拉伸应力可以利用单独使用或组合使用的一种或多种技术来实现。 在一个实施例中，可以通过在致孔剂的存在下沉积氮化硅膜来形成具有高拉伸应力的氮化硅膜。 沉积的氮化硅膜可以暴露于选自等离子体或紫外线辐射的至少一种处理以释放致孔剂。 可以使氮化硅膜致密化，使致孔剂释放产生的孔尺寸减小，并且氮化硅膜中的Si-N键变形以在氮化硅膜中产生拉伸应力。 在另一个实施例中，可以通过在低于约400℃的温度下在含氮等离子体的存在下沉积氮化硅膜来增强氮化硅膜中的拉伸应力，并将沉积的氮化硅膜暴露于紫外线 辐射。

公开(公告)号：US07566655B2

公开(公告)日：2009-07-28

申请号：US11398436

申请日：2006-04-05

申请人： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

发明人： Mihaela Balseanu ,  Jia Lee ,  Mei-Yee Shek ,  Amir Al-Bayati ,  Li-Qun Xia ,  Hichem M'Saad

IPC分类号： H01L21/44

CPC分类号： H01L29/7843 ,  C23C16/345 ,  C23C16/56 ,  H01L21/28044 ,  H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/4925 ,  H01L29/66545 ,  H01L29/66583

摘要： A process flow integration scheme employs one or more techniques to control stress in a semiconductor device formed thereby. In accordance with one embodiment, cumulative stress contributed by RTP of a nitride spacer and polysilicon gate, and subsequent deposition of a high stress etch stop layer, enhance strain and improve device performance. Germanium may be deposited or implanted into the gate structure in order to facilitate stress control.

摘要翻译： 工艺流程集成方案采用一种或多种技术来控制由此形成的半导体器件中的应力。 根据一个实施例，由氮化物间隔物和多晶硅栅极的RTP贡献的累积应力以及随后沉积高应力蚀刻停止层，增强应变并提高器件性能。 可以将锗沉积或植入栅极结构中以便于应力控制。

公开(公告)号：US20080020591A1

公开(公告)日：2008-01-24

申请号：US11762590

申请日：2007-06-13

申请人： Mihaela Balseanu ,  Victor Nguyen ,  Li-Qun Xia ,  Derek Witty ,  Hichem M'Saad ,  Mei-Yee Shek ,  Isabelita Roflox

发明人： Mihaela Balseanu ,  Victor Nguyen ,  Li-Qun Xia ,  Derek Witty ,  Hichem M'Saad ,  Mei-Yee Shek ,  Isabelita Roflox

IPC分类号： H01L21/31

CPC分类号： H01L21/3105 ,  C23C16/345 ,  C23C16/56 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3185 ,  H01L21/823807 ,  H01L29/66583 ,  H01L29/7843

摘要： Stress of a silicon nitride layer may be enhanced by deposition at higher temperatures. Employing an apparatus that allows heating of a substrate to substantially greater than 400° C. (for example a heater made from ceramic rather than aluminum), the silicon nitride film as-deposited may exhibit enhanced stress allowing for improved performance of the underlying MOS transistor device. In accordance with alternative embodiments, a deposited silicon nitride film is exposed to curing with ultraviolet (UV) radiation at an elevated temperature, thereby helping remove hydrogen from the film and increasing film stress. In accordance with still other embodiments, a silicon nitride film is formed utilizing an integrated process employing a number of deposition/curing cycles to preserve integrity of the film at the sharp corner of the underlying raised feature. Adhesion between successive layers may be promoted by inclusion of a post-UV cure plasma treatment in each cycle.

摘要翻译： 氮化硅层的应力可以通过在较高温度下沉积来增强。 使用允许将衬底加热到​​基本上大于400℃的装置（例如由陶瓷而不是铝制成的加热器），沉积的氮化硅膜可能表现出增强的应力，从而可以改善下面的MOS晶体管的性能 设备。 根据替代实施例，沉积的氮化硅膜在升高的温度下暴露于紫外线（UV）辐射固化，从而有助于从膜中除去氢并增加膜应力。 根据其他实施例，使用采用多个沉积/固化周期的整合方法形成氮化硅膜，以保持薄膜在底层凸起特征的尖角处的完整性。 可以通过在每个循环中包括UV后固化等离子体处理来促进连续层之间的粘附。

公开(公告)号：US08758638B2

公开(公告)日：2014-06-24

申请号：US13104314

申请日：2011-05-10

申请人： Weifeng Ye ,  Victor Nguyen ,  Mei-Yee Shek ,  Mihaela Balseanu ,  Li-Qun Xia ,  Derek R. Witty

发明人： Weifeng Ye ,  Victor Nguyen ,  Mei-Yee Shek ,  Mihaela Balseanu ,  Li-Qun Xia ,  Derek R. Witty

IPC分类号： H01L21/3065 ,  H01L21/302

CPC分类号： H01L21/02074 ,  H01L21/76883

摘要： A method for the removal of copper oxide from a copper and dielectric containing structure of a semiconductor chip is provided. The copper and dielectric containing structure may be planarized by chemical mechanical planarization (CMP) and treated by the method to remove copper oxide and CMP residues. Annealing in a hydrogen (H2) gas and ultraviolet (UV) environment removes copper oxide, and a pulsed ammonia plasma removes CMP residues.

摘要翻译： 提供了一种从铜中除去氧化铜和包含半导体芯片的结构的方法。 可以通过化学机械平面化（CMP）对包含铜和电介质的结构进行平面化，并通过除去氧化铜和CMP残留物的方法进行处理。 在氢（H2）气体和紫外线（UV）环境中退火除去氧化铜，脉冲氨等离子体去除CMP残留物。