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公开(公告)号：US09419217B2
公开(公告)日：2016-08-16
申请号：US13586094
申请日：2012-08-15
申请人： Lidia Vereen , Bruce Bateman , David Eggleston , Louis Parrillo
发明人： Lidia Vereen , Bruce Bateman , David Eggleston , Louis Parrillo
CPC分类号： H01L27/249 , H01L23/528 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1616
摘要： A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
摘要翻译： 一种制造存储器结构的方法包括：形成多个垂直层叠的水平线层，将多个导电垂直线与导电水平线交错，并在导电垂直线和 水平线。 在本发明的一个实施例中，导电垂直线与水平线交错，使得一排垂直线位于每个水平线层中每个水平相邻的水平线对之间。 通过配置导电垂直线和导电水平线，使得一行垂直线位于每个水平相邻的水平线对之间，可以实现仅2F2的单位存储单元覆盖区。
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公开(公告)号：US08610099B2
公开(公告)日：2013-12-17
申请号：US13586580
申请日：2012-08-15
IPC分类号： H01L21/306 , H01L29/86
CPC分类号： H01L45/145 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1666 , H01L45/1683
摘要： In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.
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公开(公告)号：US20130210211A1
公开(公告)日：2013-08-15
申请号：US13586094
申请日：2012-08-15
申请人： Lidia Vereen , Bruce Bateman , David Eggleston , Louis Parrillo
发明人： Lidia Vereen , Bruce Bateman , David Eggleston , Louis Parrillo
IPC分类号： H01L45/00
CPC分类号： H01L27/249 , H01L23/528 , H01L27/2454 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/147 , H01L45/1608 , H01L45/1616
摘要： A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.
摘要翻译： 一种制造存储器结构的方法包括：形成多个垂直层叠的水平线层，将多个导电垂直线与导电水平线交错，并在导电垂直线和 水平线。 在本发明的一个实施例中，导电垂直线与水平线交错，使得一排垂直线位于每个水平线层中每个水平相邻的一对水平线之间。 通过配置导电垂直线和导电水平线，使得一行垂直线位于每个水平相邻的水平线对之间，可以实现仅2F2的单位存储单元覆盖区。
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公开(公告)号：US20130207066A1
公开(公告)日：2013-08-15
申请号：US13586580
申请日：2012-08-15
IPC分类号： H01L45/00
CPC分类号： H01L45/145 , H01L27/2481 , H01L45/08 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16 , H01L45/1666 , H01L45/1683
摘要： In an example, a single damascene structure is formed by, for example, providing a dielectric layer, forming a void in the dielectric layer, and forming a portion of a first two-terminal resistive memory cell and a portion of a second two-terminal resistive memory cell within the void. The portions of the two-terminal resistive memory cells may be vertically stacked within the void.
摘要翻译： 在一个示例中，通过例如提供电介质层，在电介质层中形成空隙，以及形成第一两端电阻存储单元的一部分和第二两端的一部分，形成单个镶嵌结构 电阻记忆体在空隙内。 两端电阻式存储单元的部分可以垂直地堆叠在空隙内。
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公开(公告)号：US07877530B2
公开(公告)日：2011-01-25
申请号：US12619528
申请日：2009-11-16
申请人： David Eggleston
发明人： David Eggleston
IPC分类号： G06F13/14
CPC分类号： G06F13/1694 , G06F13/1678
摘要： There is provided a method and apparatus for bus negotiation. One such method includes determining a configuration of a first bond pad, the first bond pad indicating whether a host is configured to communicate with a fixed data storage device or a removable data storage device. If the first bond pad indicates the host is configured to communicate with a fixed data storage device, then the method additionally includes determining the configuration of a second bond pad. The second bond pad indicates the supported bus width of the fixed data storage device.
摘要翻译： 提供了一种用于总线协商的方法和装置。 一种这样的方法包括确定第一接合焊盘的配置，第一接合焊盘指示主机是否被配置为与固定数据存储设备或可移动数据存储设备进行通信。 如果第一接合焊盘指示主机被配置为与固定数据存储设备通信，则该方法还包括确定第二接合焊盘的配置。 第二接合焊盘表示固定数据存储设备支持的总线宽度。
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公开(公告)号：US07480762B2
公开(公告)日：2009-01-20
申请号：US11119589
申请日：2005-05-02
CPC分类号： G06F11/1008 , G06F11/1068 , G11C16/16
摘要： A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.
摘要翻译： 使用分布式擦除块扇区用户/开销数据方案详细描述了闪存设备，系统和数据处理例程，其分割用户数据和开销数据并将它们存储在不同的相关联的擦除块中。 闪速存储器的擦除块被布置成“超级块”中的相关联的擦除块对，使得当用户数据被写入/读取超块对的擦除块的扇区的用户数据区时，开销数据 被写入到/从另一个相关联的擦除块的扇区的开销数据区读取。 这种数据分割增强了闪存设备的容错能力和可靠性。
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公开(公告)号：US08719662B2
公开(公告)日：2014-05-06
申请号：US13007923
申请日：2011-01-17
申请人： David Eggleston , Bill Radke
发明人： David Eggleston , Bill Radke
IPC分类号： G11C29/00
CPC分类号： G06F11/1008
摘要： Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.
摘要翻译： 描述了能够识别数据错误的存储器件中的数据移动操作。 可以使用存储在存储器中的奇偶校验数据或ECC数据来操作存储器件中的错误检测电路。 错误检测的结果可由存储器控制器访问，用于由控制器进行数据修复操作。
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公开(公告)号：US07545682B2
公开(公告)日：2009-06-09
申请号：US11489321
申请日：2006-07-19
IPC分类号： G11C11/34
CPC分类号： G06F11/1008 , G06F11/1068 , G11C16/16
摘要： A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.
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公开(公告)号：US20070061672A1
公开(公告)日：2007-03-15
申请号：US11219535
申请日：2005-09-01
申请人： David Eggleston , Bill Radke
发明人： David Eggleston , Bill Radke
IPC分类号： H03M13/00
CPC分类号： G06F11/1008
摘要： Data move operations in a memory device are described that enable identification of data errors. Error detection circuitry in the memory device can be operated using parity data or ECC data stored in the memory. Results of the error detection can be accessed by a memory controller for data repair operations by the controller.
摘要翻译： 描述了能够识别数据错误的存储器件中的数据移动操作。 可以使用存储在存储器中的奇偶校验数据或ECC数据来操作存储器件中的错误检测电路。 错误检测的结果可由存储器控制器访问，用于由控制器进行数据修复操作。
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公开(公告)号：US20060256624A1
公开(公告)日：2006-11-16
申请号：US11489321
申请日：2006-07-19
IPC分类号： G11C7/10
CPC分类号： G06F11/1008 , G06F11/1068 , G11C16/16
摘要： A Flash memory device, system, and data handling routine is detailed with a distributed erase block sector user/overhead data scheme that splits the user data and overhead data and stores them in differing associated erase blocks. The erase blocks of the Flash memory are arranged into associated erase block pairs in “super blocks” such that when user data is written to/read from the user data area of a sector of an erase block of the super block pair, the overhead data is written to/read from the overhead data area of a sector of the other associated erase block. This data splitting enhances fault tolerance and reliability of the Flash memory device.
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