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17 条记录 (耗时 0.023 秒)

    Vertical cross-point memory arrays
    1.
    发明授权
    Vertical cross-point memory arrays 有权
    垂直交叉点存储器阵列

    公开(公告)号：US09419217B2

    公开(公告)日：2016-08-16

    申请号：US13586094

    申请日：2012-08-15

    申请人： Lidia Vereen ,  Bruce Bateman ,  David Eggleston ,  Louis Parrillo

    发明人： Lidia Vereen ,  Bruce Bateman ,  David Eggleston ,  Louis Parrillo

    IPC分类号： H01L21/20 ,  H01L45/00 ,  H01L27/24

    CPC分类号： H01L27/249 ,  H01L23/528 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1616

    摘要： A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    摘要翻译： 一种制造存储器结构的方法包括：形成多个垂直层叠的水平线层，将多个导电垂直线与导电水平线交错，并在导电垂直线和 水平线。 在本发明的一个实施例中，导电垂直线与水平线交错，使得一排垂直线位于每个水平线层中每个水平相邻的水平线对之间。 通过配置导电垂直线和导电水平线，使得一行垂直线位于每个水平相邻的水平线对之间，可以实现仅2F2的单位存储单元覆盖区。

    Vertical Cross-Point Memory Arrays
    3.
    发明申请
    Vertical Cross-Point Memory Arrays 有权
    垂直交叉点记忆阵列

    公开(公告)号：US20130210211A1

    公开(公告)日：2013-08-15

    申请号：US13586094

    申请日：2012-08-15

    申请人： Lidia Vereen ,  Bruce Bateman ,  David Eggleston ,  Louis Parrillo

    发明人： Lidia Vereen ,  Bruce Bateman ,  David Eggleston ,  Louis Parrillo

    IPC分类号： H01L45/00

    CPC分类号： H01L27/249 ,  H01L23/528 ,  H01L27/2454 ,  H01L45/08 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1608 ,  H01L45/1616

    摘要： A method of manufacturing a memory structure includes forming a plurality of vertically-stacked horizontal line layers, interleaving a plurality of electrically conductive vertical lines with the electrically conductive horizontal lines, and forming a memory film at and between intersections of the electrically conductive vertical lines and the horizontal lines. In one embodiment of the invention, the electrically conductive vertical lines are interleaved with the horizontal lines such that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines in each horizontal line layer. By configuring the electrically conductive vertical lines and electrically conductive horizontal lines so that a row of vertical lines is positioned between each horizontally-adjacent pair of horizontal lines, a unit memory cell footprint of just 2F2 may be realized.

    摘要翻译： 一种制造存储器结构的方法包括：形成多个垂直层叠的水平线层，将多个导电垂直线与导电水平线交错，并在导电垂直线和 水平线。 在本发明的一个实施例中，导电垂直线与水平线交错，使得一排垂直线位于每个水平线层中每个水平相邻的一对水平线之间。 通过配置导电垂直线和导电水平线，使得一行垂直线位于每个水平相邻的水平线对之间，可以实现仅2F2的单位存储单元覆盖区。

    System and method to implement a matrix multiply unit of a broadband processor
    5.
    发明授权
    System and method to implement a matrix multiply unit of a broadband processor 失效
    实现宽带处理器的矩阵乘法单元的系统和方法

    公开(公告)号：US08195735B2

    公开(公告)日：2012-06-05

    申请号：US12330962

    申请日：2008-12-09

    申请人： Craig Hansen ,  Bruce Bateman ,  John Moussouris

    发明人： Craig Hansen ,  Bruce Bateman ,  John Moussouris

    IPC分类号： G06F7/52 ,  G06F7/38

    CPC分类号： G06F7/5338 ,  G06F7/4812 ,  G06F7/49994 ,  G06F7/57 ,  G06F7/724 ,  G06F9/30014 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/16 ,  G06F2207/3812 ,  G06F2207/382 ,  G06F2207/3824 ,  G06F2207/3828

    摘要： The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

    摘要翻译： 本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。 功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。 该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

    SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR
    6.
    发明申请
    SYSTEM AND METHOD TO IMPLEMENT A MATRIX MULTIPLY UNIT OF A BROADBAND PROCESSOR 失效
    用于实现宽带处理器的矩阵多项式单元的系统和方法

    公开(公告)号：US20090094309A1

    公开(公告)日：2009-04-09

    申请号：US12330962

    申请日：2008-12-09

    申请人： Craig HANSEN ,  Bruce Bateman ,  John Moussouris

    发明人： Craig HANSEN ,  Bruce Bateman ,  John Moussouris

    IPC分类号： G06F7/38 ,  G06F7/52

    CPC分类号： G06F7/5338 ,  G06F7/4812 ,  G06F7/49994 ,  G06F7/57 ,  G06F7/724 ,  G06F9/30014 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/16 ,  G06F2207/3812 ,  G06F2207/382 ,  G06F2207/3824 ,  G06F2207/3828

    摘要： The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

    摘要翻译： 本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。 功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。 该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

    Memory array with local bitlines and local-to-global bitline pass gates and gain stages
    7.
    发明授权
    Memory array with local bitlines and local-to-global bitline pass gates and gain stages 有权
    具有本地位线和本地到全局位线传递门​​和增益级的存储器阵列

    公开(公告)号：US08891276B2

    公开(公告)日：2014-11-18

    申请号：US13134579

    申请日：2011-06-10

    申请人： Chang Hua Siau ,  Bruce Bateman

    发明人： Chang Hua Siau ,  Bruce Bateman

    IPC分类号： G11C5/06 ,  G11C13/00 ,  G11C16/00 ,  G11C7/18 ,  G11C7/00

    CPC分类号： G11C5/06 ,  G11C7/00 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C16/00 ,  G11C2213/71

    摘要： A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.

    摘要翻译： 存储器阵列包括字线，本地位线，双端存储器元件，全局位线以及局部到全局位线传递门​​和增益级。 存储元件形成在字线和本地位线之间。 每个本地位线通过相关联的局部到全局位线传递门​​选择性地耦合到相关联的全局位线。 在选择本地位线的存储元件被读取的读取操作期间，局部到全局增益级被配置为将本地位线上的信号放大到相关联的全局位线上或沿相关联的全局位线 。 在一个实施例中放大的信号取决于所选择的存储器元件的电阻状态，被用于快速地确定由所选择的存储器元件存储的存储器状态。

    Memory array with local bitlines and local-to-global bitline pass gates and gain stages
    9.
    发明申请
    Memory array with local bitlines and local-to-global bitline pass gates and gain stages 有权
    具有本地位线和本地到全局位线传递门​​和增益级的存储器阵列

    公开(公告)号：US20120314468A1

    公开(公告)日：2012-12-13

    申请号：US13134579

    申请日：2011-06-10

    申请人： Chang Hua Siau ,  Bruce Bateman

    发明人： Chang Hua Siau ,  Bruce Bateman

    IPC分类号： G11C5/06 ,  G11C5/08 ,  B82Y10/00

    CPC分类号： G11C5/06 ,  G11C7/00 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0026 ,  G11C16/00 ,  G11C2213/71

    摘要： A memory array includes wordlines, local bitlines, two-terminal memory elements, global bitlines, and local-to-global bitline pass gates and gain stages. The memory elements are formed between the wordlines and local bitlines. Each local bitline is selectively coupled to an associated global bitline, by way of an associated local-to-global bitline pass gate. During a read operation when a memory element of a local bitline is selected to be read, a local-to-global gain stage is configured to amplify a signal on or passing through the local bitline to an amplified signal on or along an associated global bitline. The amplified signal, which in one embodiment is dependent on the resistive state of the selected memory element, is used to rapidly determine the memory state stored by the selected memory element.

    摘要翻译： 存储器阵列包括字线，本地位线，双端存储器元件，全局位线以及局部到全局位线传递门​​和增益级。 存储元件形成在字线和本地位线之间。 每个本地位线通过相关联的局部到全局位线传递门​​选择性地耦合到相关联的全局位线。 在选择本地位线的存储元件被读取的读取操作期间，局部到全局增益级被配置为将本地位线上的信号放大到相关联的全局位线上或沿相关联的全局位线 。 在一个实施例中放大的信号取决于所选择的存储器元件的电阻状态，被用于快速地确定由所选择的存储器元件存储的存储器状态。