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7 条记录 (耗时 0.013 秒)

    Time based data separator zone change sequence
    1.
    发明授权
    Time based data separator zone change sequence 失效
    基于时间的数据分隔区更改顺序

    公开(公告)号：US5351015A

    公开(公告)日：1994-09-27

    申请号：US12914

    申请日：1993-02-03

    申请人： Rodney T. Masumoto ,  Shunsaku Ueda ,  Jenn-Gang Chern ,  Kirby Lam

    发明人： Rodney T. Masumoto ,  Shunsaku Ueda ,  Jenn-Gang Chern ,  Kirby Lam

    IPC分类号： G11B20/12 ,  G11B20/14 ,  H03L3/00 ,  H03L7/089 ,  H03L7/189 ,  H03L7/00

    CPC分类号： G11B20/1403 ,  H03L3/00 ,  H03L7/0891 ,  H03L7/189 ,  G11B20/1258 ,  H03L2207/06

    摘要： The present invention provides a method and an apparatus for controlling initial transients in a frequency synthesizer by controlling the start-up sequence of the device. The start-up sequence comprises several steps. The voltage controlled oscillator(s) (VCO) is reset so that the VCO(s) are in a known state during start-up. The charge pump and phase detector of phase-locked loop (PLL) are disabled. New data values are loaded into counter(s)/register(s) that control the frequency of the VCO(s). Also, a data value is provided to a digital-to-analog converter (DAC) to set the data rate for the PLL. A fixed amount of time is provided as a delay for the DAC to settle (i.e., 1.6 .mu.s). Divide-by-M and divide-by-N counters are then enabled. Also, the phase detector of the phase-locked loop (PLL) is enabled. The VCO is then restarted. By utilizing a start-up sequence, the center frequency of the VCO is already settled when changing frequencies, the divide-by-M and divide-by-N counters are matched, the VCO starts in phase with the reference frequency of the reference signal, and the voltage of the loop filter is prevented from railing. By using dual buffered registers for each counter, loading of the divide-by-M and divide-by-N counters is accomplished without shutting down the VCO. A timer provides a 1.6 .mu.s delay to allow the DAC to settle. Digital logic is used to synchronize signals. Delay compensation circuitry is used to implement delay cancellation for zero phase restart.

    摘要翻译： 本发明提供一种通过控制装置启动顺序来控制频率合成器中的初始瞬变的方法和装置。 启动顺序包括几个步骤。 压控振荡器（VCO）被复位，使得VCO在启动期间处于已知状态。 锁相环（PLL）的电荷泵和相位检测器被禁用。 新的数据值被加载到控制VCO频率的计数器/寄存器中。 另外，将数据值提供给数模转换器（DAC）以设置PLL的数据速率。 提供固定的时间量作为DAC稳定的延迟（即1.6μs）。 然后启用除以M和N分频计数器。 此外，锁相环（PLL）的相位检测器使能。 然后重新启动VCO。 通过利用启动序列，VCO的中心频率在改变频率时已经稳定，除以M和除以N的计数器相匹配，VCO与参考信号的参考频率同相启动 ，并且防止环路滤波器的电压进行栏杆。 通过对每个计数器使用双缓冲寄存器，可以在不关闭VCO的情况下完成M分频和N分频计数器的加载。 一个定时器提供1.6μs的延迟以允许DAC稳定。 数字逻辑用于同步信号。 延迟补偿电路用于实现零相重启的延迟消除。

    Frequency and capacitor based constant current source
    2.
    发明授权
    Frequency and capacitor based constant current source 失效
    基于频率和电容器的恒定电流源

    公开(公告)号：US5247241A

    公开(公告)日：1993-09-21

    申请号：US780153

    申请日：1991-10-21

    申请人： Shunsaku Ueda

    发明人： Shunsaku Ueda

    IPC分类号： G05F1/10 ,  G05F3/26 ,  H02M3/07

    CPC分类号： H02M3/07 ,  Y10S331/02

    摘要： The present invention is a constant current source whose magnitude is proportional to capacitor values, reference voltage and input frequency. A frequency divider provides a plurality of signals to one of a plurality of capacitor switches located within a charge generator. The outputs of the capacitor switches are combined to provide a known charge Q.sub.i to an output generator at regular intervals, t.sub.0 =1/F.sub.in. The output generator produces an output current I.sub.out =Q.sub.i /t.sub.0 =C.sub.i *V.sub.bg *F.sub.in, where C.sub.i is a capacitor value, V.sub.bg is a reference voltage, and F.sub.in is the input frequency. A controller provides a control signal to the output generator to limit variations in the output current I.sub.out. The preferred embodiment may be used in conjunction with process invariant circuits in a variety of semiconductor technologies: CMOS, Bipolar, BiCMOS and GAS. In one embodiment, the present invention is used in conjuction with a timer/delay circuit. In another embodiment, the present invention is used in conjunction with a calibration circuit to compensate for various inaccuracies in component performance.

    摘要翻译： 本发明是恒定电流源，其幅度与电容器值，参考电压和输入频率成比例。 分频器向位于电荷发生器内的多个电容器开关中的一个提供多个信号。 组合电容器开关的输出，以规定的间隔向输出发生器提供已知的电荷Qi，t0 = 1 / Fin。 输出发生器产生输出电流Iout = Qi / t0 = Ci * Vbg * Fin，其中Ci是电容值，Vbg是参考电压，Fin是输入频率。 控制器向输出发生器提供控制信号以限制输出电流Iout的变化。 优选实施例可以与各种半导体技术中的工艺不变电路结合使用：CMOS，双极，BiCMOS和GAS。 在一个实施例中，本发明与定时器/延迟电路结合使用。 在另一个实施例中，本发明与校准电路结合使用以补偿组件性能中的各种不准确性。

    Zero phase restart compensation for VCO
    4.
    发明授权
    Zero phase restart compensation for VCO 失效
    VCO的零相重启补偿

    公开(公告)号：US5065116A

    公开(公告)日：1991-11-12

    申请号：US646867

    申请日：1991-01-28

    申请人： Shunsaku Ueda ,  Rodney T. Masumoto

    发明人： Shunsaku Ueda ,  Rodney T. Masumoto

    IPC分类号： H03L7/08 ,  H03L7/10

    CPC分类号： H03L7/10

    摘要： A zero-phase restart circuit that provides a new circuit element in the path of the incoming data signal in order to delay the data signal by an amount equal to the delay caused by the restart circuitry. This ensures that the phase difference between the two signals will be zero at restart and thus effectively cancels out the residual error seen with the prior art. This technique remains effective well into higher data rates. The advantages of the present invention allows the circuit to operate near its limit without suffering large transients on the VCO control voltage and the VCO frequency. The overall system will not be limited by the transient response on the VCO control voltage nor the VCO frequency. It allows for higher operating speeds of data. Further, the new method will allow the system to better tolerate the jitter of the incoming data such that the restrictions on the jitter performance of the incoming data can be reduced substantially, i.e., allow more jitter to exist on the data.

    摘要翻译： 零相重启电路，在输入数据信号的路径中提供新的电路元件，以便将数据信号延迟等于由重启电路引起的延迟量。 这确保了重启时两个信号之间的相位差将为零，因此有效地消除了现有技术所看到的残余误差。 这种技术在更高的数据速率方面仍然有效。 本发明的优点允许电路在其极限附近工作，而不会在VCO控制电压和VCO频率上遭受大的瞬变。 整个系统不受VCO控制电压和VCO频率的瞬态响应的限制。 它允许更高的数据操作速度。 此外，新方法将允许系统更好地容忍输入数据的抖动，使得可以显着地减少输入数据的抖动性能的限制，即允许在数据上存在更多的抖动。

    High speed threshold crossing detector with reset
    5.
    发明授权
    High speed threshold crossing detector with reset 失效
    具有复位功能的高速阈值检测器

    公开(公告)号：US5311071A

    公开(公告)日：1994-05-10

    申请号：US779963

    申请日：1991-10-21

    申请人： Shunsaku Ueda

    发明人： Shunsaku Ueda

    IPC分类号： G01R19/165 ,  G05F3/26 ,  H03K5/08 ,  H03K5/24 ,  H03L7/099 ,  H03K17/04

    CPC分类号： G01R19/16519 ,  G05F3/262 ,  H03K5/2481 ,  H03L7/099

    摘要： The present invention provides a high speed, all CMOS comparator utilizing positive feedback and DC voltage clamping. The circuit comprises two source-coupled PMOS transistors with their sources coupled to a current source or a supply voltage. A third PMOS transistor is coupled between the source of the first PMOS transistor and a terminal of a current mirror. The gate of this third PMOS transistor is coupled to the output node in such a way as to provide positive feedback to the circuit. As the negative input voltage becomes lower than the positive input voltage, the current passing through the second PMOS transistor increases and the current passing through the first PMOS transistor decreases. As the output node increases in voltage, the equivalent resistance of the third PMOS transistor increases, thus decreasing the current through the first PMOS transistor. This acts to increase the current being provided to the output node and increases the drive characteristics of the circuit. As a further improvement to the circuit, a voltage-clamping device is included in the design.

    摘要翻译： 本发明提供一种利用正反馈和直流电压钳位的高速全CMOS应用比较器。 电路包括两个源极耦合PMOS晶体管，其源极耦合到电流源或电源电压。 第三PMOS晶体管耦合在第一PMOS晶体管的源极和电流镜的端子之间。 该第三PMOS晶体管的栅极以向电路提供正反馈的方式耦合到输出节点。 当负输入电压变得低于正输入电压时，通过第二PMOS晶体管的电流增加，并且通过第一PMOS晶体管的电流减小。 随着输出节点电压增加，第三PMOS晶体管的等效电阻增加，从而减小了通过第一PMOS晶体管的电流。 这用于增加提供给输出节点的电流并增加电路的驱动特性。 作为电路的进一步改进，设计中包括电压钳位装置。

    Linearized and delay compensated all CMOS VCO
    6.
    发明授权
    Linearized and delay compensated all CMOS VCO 失效
    线性化和延迟补偿的所有CMOS VCO

    公开(公告)号：US5212459A

    公开(公告)日：1993-05-18

    申请号：US960534

    申请日：1992-10-13

    申请人： Shunsaku Ueda ,  Kwai-Kwong Lam ,  Craig Robertson

    发明人： Shunsaku Ueda ,  Kwai-Kwong Lam ,  Craig Robertson

    IPC分类号： H03K3/0231

    CPC分类号： H03K3/0231

    摘要： The present invention provides a linearized and delay compensated all CMOS voltage controlled oscillator. A transconductance converter receives a control voltage input and provides a control current to a current controlled ramping circuit that is responsible for providing two ramping voltage outputs to the positive inputs of two comparators. These comparators compare the ramping voltages to a threshold voltage and provide pulses to a latch when the ramping voltages cross the threshold voltage. The latch provides the oscillating output of the circuit which is fed back to the current controlled ramping circuit for switching purposes. A compensation loop receives both the oscillating output of the latch and the control current as inputs and provides the threshold voltage to the comparators. The compensation loop contains a similar current controlled ramping circuit which provides ramping outputs identical to those of the first current controlled ramping circuit. Track-and-hold circuits triggered by the oscillating outputs provide the peak voltages of the ramping outputs through a low-pass filter to the negative input of a difference amplifier. An external reference voltage is supplied to the positive input of the difference amplifier and the output of the difference amplifier is provided as the threshold voltage to the comparators. The effects of the comparator delay and the latch delay are cancelled out by the compensation loop.

    摘要翻译： 本发明提供一种线性化和延迟补偿的全部CMOS压控振荡器。 跨导转换器接收控制电压输入并向控制的电流斜坡电路提供控制电流，该电路负责向两个比较器的正输入端提供两个斜坡电压输出。 这些比较器将斜坡电压与阈值电压进行比较，并且当斜坡电压跨越阈值电压时，向闩锁提供脉冲。 闩锁提供电路的振荡输出，其被反馈到电流控制的斜坡电路以用于切换目的。 补偿回路接收锁存器的振荡输出和控制电流作为输入，并将阈值电压提供给比较器。 补偿回路包含类似的电流控制斜坡电路，其提供与第一电流控制斜坡电路相同的斜坡输出。 由振荡输出触发的跟踪和保持电路通过低通滤波器向差分放大器的负输入提供斜坡输出的峰值电压。 外部参考电压被提供给差分放大器的正输入，差分放大器的输出作为阈值电压被提供给比较器。 比较器延迟和锁存延迟的影响由补偿回路消除。

    Linearized and delay compensated all CMOS VCO
    7.
    发明授权
    Linearized and delay compensated all CMOS VCO 失效
    线性化和延迟补偿的所有CMOS VCO

    公开(公告)号：US5155452A

    公开(公告)日：1992-10-13

    申请号：US792222

    申请日：1991-11-12

    申请人： Shunsaku Ueda ,  Kwai-Kwong Lam ,  Craig Robertson

    发明人： Shunsaku Ueda ,  Kwai-Kwong Lam ,  Craig Robertson

    IPC分类号： H03K4/12 ,  H03K3/0231 ,  H03L7/099

    CPC分类号： H03K3/0231

    摘要： The present invention provides a linearized and delay compensated all CMOS voltage controlled oscillator. A transconductance converter receives a control voltage input and provides a control current to a current controlled ramping circuit that is responsible for providing two ramping voltage outputs to the positive inputs of two comparators. These comparators compare the ramping voltages to a threshold voltage and provide pulses to a latch when the ramping voltages cross the threshold voltage. The latch provides the oscillating output of the circuit which is fed back to the current controlled ramping circuit for switching purposes. A compensation loop receives both the oscillating output of the latch and the control current as inputs and provides the threshold voltage to the comparators. The compensation loop contains a similar current controlled ramping circuit which provides ramping outputs identical to those of the first current controlled ramping circuit. Track-and-hold circuits triggered by the oscillating outputs provide the peak voltages of the ramping outputs through a low-pass filter to the negative input of a difference amplifier. An external reference voltage is supplied to the positive input of the difference amplifier and the output of the difference amplifier is provided as the threshold voltage to the comparators. The effects of the comparator delay and the latch delay are cancelled out by the compensation loop.

    摘要翻译： 本发明提供一种线性化和延迟补偿的全部CMOS压控振荡器。 跨导转换器接收控制电压输入并向控制的电流斜坡电路提供控制电流，该电路负责向两个比较器的正输入端提供两个斜坡电压输出。 这些比较器将斜坡电压与阈值电压进行比较，并且当斜坡电压跨越阈值电压时，向闩锁提供脉冲。 闩锁提供电路的振荡输出，其被反馈到电流控制的斜坡电路以用于切换目的。 补偿回路接收锁存器的振荡输出和控制电流作为输入，并将阈值电压提供给比较器。 补偿回路包含类似的电流控制斜坡电路，其提供与第一电流控制斜坡电路相同的斜坡输出。 由振荡输出触发的跟踪和保持电路通过低通滤波器向差分放大器的负输入提供斜坡输出的峰值电压。 外部参考电压被提供给差分放大器的正输入，差分放大器的输出作为阈值电压被提供给比较器。 比较器延迟和锁存延迟的影响由补偿回路消除。