公开(公告)号：US12004351B2

公开(公告)日：2024-06-04

申请号：US17869732

申请日：2022-07-20

申请人： Lodestar Licensing Group LLC

发明人： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC分类号： H10B43/27 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H01L21/768

CPC分类号： H10B43/27 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0466 ,  H01L21/76802 ,  H01L21/76877

摘要： Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20240324223A1

公开(公告)日：2024-09-26

申请号：US18731940

申请日：2024-06-03

申请人： Lodestar Licensing Group LLC

发明人： S. M. Istiaque Hossain ,  Prakash Rau Mokhna Rau ,  Arun Kumar Dhayalan ,  Damir Fazil ,  Joel D. Peterson ,  Anilkumar Chandolu ,  Albert Fayrushin ,  George Matamis ,  Christopher Larsen ,  Rokibul Islam

IPC分类号： H10B43/27 ,  G11C5/02 ,  G11C5/06 ,  G11C16/04 ,  H01L21/768

CPC分类号： H10B43/27 ,  G11C5/025 ,  G11C5/06 ,  G11C16/0466 ,  H01L21/76802 ,  H01L21/76877

摘要： Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.